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fpga: x400: Split DRAM interface on X440_X4_200

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Original-commit: 9001c6638086b3383a057f7a994687a8abad5e99
This commit is contained in:
Wade Fife
2023-10-25 12:49:38 -05:00
parent 02f2a821f9
commit e67c1f9ed4
1 changed files with 93 additions and 47 deletions
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top/x400/x440_200_rfnoc_image_core.v
+93 -47
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@@ -36,12 +36,12 @@ module rfnoc_image_core #(
input wire chdr_aclk,
input wire ctrl_aclk,
input wire core_arst,
input wire ce_clk,
input wire radio0_clk,
input wire radio1_clk,
input wire radio0_2x_clk,
input wire radio1_2x_clk,
input wire dram_clk,
input wire ce_clk,
// Basic
input wire [ 15:0] device_id,
@@ -87,52 +87,98 @@ module rfnoc_image_core #(
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
output wire [ 23:0] m_axi_awsize,
output wire [ 15:0] m_axi_awburst,
output wire [ 7:0] m_axi_awlock,
output wire [ 31:0] m_axi_awcache,
output wire [ 23:0] m_axi_awprot,
output wire [ 31:0] m_axi_awqos,
output wire [ 31:0] m_axi_awregion,
output wire [ 7:0] m_axi_awuser,
output wire [ 7:0] m_axi_awvalid,
input wire [ 7:0] m_axi_awready,
output wire [4191:0] m_axi_wdata,
output wire [ 511:0] m_axi_wstrb,
output wire [ 7:0] m_axi_wlast,
output wire [ 7:0] m_axi_wuser,
output wire [ 7:0] m_axi_wvalid,
input wire [ 7:0] m_axi_wready,
input wire [ 7:0] m_axi_bid,
input wire [ 15:0] m_axi_bresp,
input wire [ 7:0] m_axi_buser,
input wire [ 7:0] m_axi_bvalid,
output wire [ 7:0] m_axi_bready,
output wire [ 7:0] m_axi_arid,
output wire [ 383:0] m_axi_araddr,
output wire [ 63:0] m_axi_arlen,
output wire [ 23:0] m_axi_arsize,
output wire [ 15:0] m_axi_arburst,
output wire [ 7:0] m_axi_arlock,
output wire [ 31:0] m_axi_arcache,
output wire [ 31:0] m_axi_arprot,
output wire [ 31:0] m_axi_arqos,
output wire [ 31:0] m_axi_arregion,
output wire [ 7:0] m_axi_aruser,
output wire [ 7:0] m_axi_arvalid,
input wire [ 7:0] m_axi_arready,
input wire [ 7:0] m_axi_rid,
input wire [4191:0] m_axi_rdata,
input wire [ 15:0] m_axi_rresp,
input wire [ 7:0] m_axi_rlast,
input wire [ 7:0] m_axi_ruser,
input wire [ 7:0] m_axi_rvalid,
output wire [ 7:0] m_axi_rready,
// dram0
input wire [ 0:0] dram0_axi_rst,
output wire [ 7:0] dram0_m_axi_awid,
output wire [ 383:0] dram0_m_axi_awaddr,
output wire [ 63:0] dram0_m_axi_awlen,
output wire [ 23:0] dram0_m_axi_awsize,
output wire [ 15:0] dram0_m_axi_awburst,
output wire [ 7:0] dram0_m_axi_awlock,
output wire [ 31:0] dram0_m_axi_awcache,
output wire [ 23:0] dram0_m_axi_awprot,
output wire [ 31:0] dram0_m_axi_awqos,
output wire [ 31:0] dram0_m_axi_awregion,
output wire [ 7:0] dram0_m_axi_awuser,
output wire [ 7:0] dram0_m_axi_awvalid,
input wire [ 7:0] dram0_m_axi_awready,
output wire [4191:0] dram0_m_axi_wdata,
output wire [ 511:0] dram0_m_axi_wstrb,
output wire [ 7:0] dram0_m_axi_wlast,
output wire [ 7:0] dram0_m_axi_wuser,
output wire [ 7:0] dram0_m_axi_wvalid,
input wire [ 7:0] dram0_m_axi_wready,
input wire [ 7:0] dram0_m_axi_bid,
input wire [ 15:0] dram0_m_axi_bresp,
input wire [ 7:0] dram0_m_axi_buser,
input wire [ 7:0] dram0_m_axi_bvalid,
output wire [ 7:0] dram0_m_axi_bready,
output wire [ 7:0] dram0_m_axi_arid,
output wire [ 383:0] dram0_m_axi_araddr,
output wire [ 63:0] dram0_m_axi_arlen,
output wire [ 23:0] dram0_m_axi_arsize,
output wire [ 15:0] dram0_m_axi_arburst,
output wire [ 7:0] dram0_m_axi_arlock,
output wire [ 31:0] dram0_m_axi_arcache,
output wire [ 31:0] dram0_m_axi_arprot,
output wire [ 31:0] dram0_m_axi_arqos,
output wire [ 31:0] dram0_m_axi_arregion,
output wire [ 7:0] dram0_m_axi_aruser,
output wire [ 7:0] dram0_m_axi_arvalid,
input wire [ 7:0] dram0_m_axi_arready,
input wire [ 7:0] dram0_m_axi_rid,
input wire [4191:0] dram0_m_axi_rdata,
input wire [ 15:0] dram0_m_axi_rresp,
input wire [ 7:0] dram0_m_axi_rlast,
input wire [ 7:0] dram0_m_axi_ruser,
input wire [ 7:0] dram0_m_axi_rvalid,
output wire [ 7:0] dram0_m_axi_rready,
// dram1
input wire [ 0:0] dram1_axi_rst,
output wire [ 7:0] dram1_m_axi_awid,
output wire [ 383:0] dram1_m_axi_awaddr,
output wire [ 63:0] dram1_m_axi_awlen,
output wire [ 23:0] dram1_m_axi_awsize,
output wire [ 15:0] dram1_m_axi_awburst,
output wire [ 7:0] dram1_m_axi_awlock,
output wire [ 31:0] dram1_m_axi_awcache,
output wire [ 23:0] dram1_m_axi_awprot,
output wire [ 31:0] dram1_m_axi_awqos,
output wire [ 31:0] dram1_m_axi_awregion,
output wire [ 7:0] dram1_m_axi_awuser,
output wire [ 7:0] dram1_m_axi_awvalid,
input wire [ 7:0] dram1_m_axi_awready,
output wire [4191:0] dram1_m_axi_wdata,
output wire [ 511:0] dram1_m_axi_wstrb,
output wire [ 7:0] dram1_m_axi_wlast,
output wire [ 7:0] dram1_m_axi_wuser,
output wire [ 7:0] dram1_m_axi_wvalid,
input wire [ 7:0] dram1_m_axi_wready,
input wire [ 7:0] dram1_m_axi_bid,
input wire [ 15:0] dram1_m_axi_bresp,
input wire [ 7:0] dram1_m_axi_buser,
input wire [ 7:0] dram1_m_axi_bvalid,
output wire [ 7:0] dram1_m_axi_bready,
output wire [ 7:0] dram1_m_axi_arid,
output wire [ 383:0] dram1_m_axi_araddr,
output wire [ 63:0] dram1_m_axi_arlen,
output wire [ 23:0] dram1_m_axi_arsize,
output wire [ 15:0] dram1_m_axi_arburst,
output wire [ 7:0] dram1_m_axi_arlock,
output wire [ 31:0] dram1_m_axi_arcache,
output wire [ 31:0] dram1_m_axi_arprot,
output wire [ 31:0] dram1_m_axi_arqos,
output wire [ 31:0] dram1_m_axi_arregion,
output wire [ 7:0] dram1_m_axi_aruser,
output wire [ 7:0] dram1_m_axi_arvalid,
input wire [ 7:0] dram1_m_axi_arready,
input wire [ 7:0] dram1_m_axi_rid,
input wire [4191:0] dram1_m_axi_rdata,
input wire [ 15:0] dram1_m_axi_rresp,
input wire [ 7:0] dram1_m_axi_rlast,
input wire [ 7:0] dram1_m_axi_ruser,
input wire [ 7:0] dram1_m_axi_rvalid,
output wire [ 7:0] dram1_m_axi_rready,
// Transport Adapters ///////////////