From e44fe8625bdd8d64d9add46c0dc72a8b97d92671 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Fri, 27 Oct 2023 12:03:46 +0200 Subject: [PATCH] fpga: lib: Add default wiretypes to synchronizer The module was failing with missing wire types when instantiated from another module with a default wiretype of 'none'. To fix this, this module was also moved to no default wire type. Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a --- lib/control/synchronizer.v | 12 ++++++++---- lib/control/synchronizer_impl.v | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/lib/control/synchronizer.v b/lib/control/synchronizer.v index 6ac1601..c3cf944 100644 --- a/lib/control/synchronizer.v +++ b/lib/control/synchronizer.v @@ -43,16 +43,18 @@ // tool analyze this path. // +`default_nettype none + module synchronizer #( parameter WIDTH = 1, parameter STAGES = 2, parameter INITIAL_VAL = 0, parameter FALSE_PATH_TO_IN = 1 )( - input clk, - input rst, - input [WIDTH-1:0] in, - output [WIDTH-1:0] out + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out ); generate if (FALSE_PATH_TO_IN == 1) begin @@ -70,3 +72,5 @@ module synchronizer #( end endgenerate endmodule //synchronizer +// +`default_nettype wire diff --git a/lib/control/synchronizer_impl.v b/lib/control/synchronizer_impl.v index 1c4f777..98fdc92 100644 --- a/lib/control/synchronizer_impl.v +++ b/lib/control/synchronizer_impl.v @@ -5,15 +5,17 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // +`default_nettype none + module synchronizer_impl #( parameter WIDTH = 1, parameter STAGES = 2, parameter INITIAL_VAL = 0 )( - input clk, - input rst, - input [WIDTH-1:0] in, - output [WIDTH-1:0] out + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out ); (* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] value[0:STAGES-1]; @@ -45,3 +47,5 @@ module synchronizer_impl #( assign out = value[STAGES-1]; endmodule //synchronizer_impl + +`default_nettype wire