fpga: lib: Add interface and model for AXI4-Lite

(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
    and an AxiLiteBfm class.

Important Methods
  a. wr - performs non-blocking write and checks for expected response
  b. wr_block - performs a blocking write and provides response
  c. rd - performs a non-blocking read and checks for expected response
  d. rd_block - persforms a blocking read  and provides response

The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods.  When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.


Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a

lib/axi4lite_sv/Makefile.srcs

@@ -0,0 +1,13 @@
+#
+# Copyright 2020 Ettus Research, A National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Utility Sources
+##################################################
+AXI4LITE_SV_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/axi4lite_sv/, \
+PkgAxiLite.sv \
+AxiLiteIf.sv \
+))