From ddbff804ed39daf1a6f051df42d72e0b20835a52 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Tue, 24 Oct 2023 07:02:51 -0500 Subject: [PATCH] fpga: x400: update signals to run on two domains Original-commit: 982ea5b2d85c5a120569d80be3c53b54fdd670d3 --- .../x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl | 129 +++++++++--------- top/x400/rfdc_timing_control.v | 78 +++++++---- top/x400/x4xx.v | 56 ++++---- top/x400/x4xx_core.v | 8 +- top/x400/x4xx_core_common.v | 82 +++++++++-- 5 files changed, 217 insertions(+), 136 deletions(-) diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl index e6a04ee..e33b677 100644 --- a/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl @@ -872,24 +872,26 @@ proc create_hier_cell_rfdc { parentCell nameHier } { # Create pins - create_bd_pin -dir O -from 0 -to 0 adc_data_out_resetn_dclk - create_bd_pin -dir O adc_enable_data_rclk - create_bd_pin -dir I adc_reset_pulse_dclk - create_bd_pin -dir O adc_rfdc_axi_resetn_rclk + create_bd_pin -dir O adc_enable_data_r0clk + create_bd_pin -dir O adc_enable_data_r1clk + create_bd_pin -dir I adc_reset_pulse_r0clk + create_bd_pin -dir I adc_reset_pulse_r1clk + create_bd_pin -dir O adc_rfdc_axi_resetn_r0clk + create_bd_pin -dir O adc_rfdc_axi_resetn_r1clk create_bd_pin -dir O clk_adc0 - create_bd_pin -dir O -from 0 -to 0 dac_data_in_resetn_dclk - create_bd_pin -dir O -from 0 -to 0 dac_data_in_resetn_dclk2x - create_bd_pin -dir O dac_data_in_resetn_rclk - create_bd_pin -dir O dac_data_in_resetn_rclk2x - create_bd_pin -dir I dac_reset_pulse_dclk + create_bd_pin -dir O dac_data_in_resetn_r0clk + create_bd_pin -dir O dac_data_in_resetn_r0clk2x + create_bd_pin -dir O dac_data_in_resetn_r1clk + create_bd_pin -dir O dac_data_in_resetn_r1clk2x + create_bd_pin -dir I dac_reset_pulse_r0clk + create_bd_pin -dir I dac_reset_pulse_r1clk create_bd_pin -dir O -type clk data_clk create_bd_pin -dir O -type clk data_clk_2x create_bd_pin -dir O data_clock_locked create_bd_pin -dir I enable_gated_clocks_clk40 - create_bd_pin -dir I enable_sysref_rclk - create_bd_pin -dir O fir_resetn_rclk2x + create_bd_pin -dir I enable_sysref_r0clk create_bd_pin -dir O gated_base_clks_valid_clk40 - create_bd_pin -dir O nco_reset_done_dclk + create_bd_pin -dir O nco_reset_done_r0clk create_bd_pin -dir I -type clk pll_ref_clk_in create_bd_pin -dir O -type clk pll_ref_clk_out create_bd_pin -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk @@ -906,9 +908,9 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_bd_pin -dir O -type intr rfdc_irq create_bd_pin -dir I -type rst s_axi_config_aresetn create_bd_pin -dir I -type clk s_axi_config_clk - create_bd_pin -dir I start_nco_reset_dclk + create_bd_pin -dir I start_nco_reset_r0clk create_bd_pin -dir O sysref_out_pclk - create_bd_pin -dir O sysref_out_rclk + create_bd_pin -dir O sysref_out_r0clk create_bd_pin -dir I sysref_pl_in # Create instance: ThresholdRegister @@ -1508,9 +1510,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } { CONFIG.DOUT_WIDTH {4} \ ] $slice_iqswap_3_0_radio1 - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - # Create interface connections connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_pins axi_interconnect_rf/M06_AXI] [get_bd_intf_pins calibration_muxes/S_AXI_1] connect_bd_intf_net -intf_net adc0_clk_0_1 [get_bd_intf_pins adc0_clk] [get_bd_intf_pins rf_data_converter/adc0_clk] @@ -1584,8 +1583,9 @@ proc create_hier_cell_rfdc { parentCell nameHier } { # Create port connections connect_bd_net -net M02_ARESETN_1 [get_bd_pins axi_interconnect_rf/M02_ARESETN] [get_bd_pins axi_interconnect_rf/M11_ARESETN] [get_bd_pins const_1/dout] [get_bd_pins reg_invert_iq_radio0/s_axi_aresetn] [get_bd_pins reg_invert_iq_radio1/s_axi_aresetn] - connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_pins adc_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/rAdcResetPulse] [get_bd_pins rf_reset_controller_1/rAdcResetPulse] - connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_rclk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] [get_bd_pins rf_nco_reset_0/dSysref] + connect_bd_net -net adc_reset_pulse_r0clk_1 [get_bd_pins adc_reset_pulse_r0clk] [get_bd_pins rf_reset_controller_0/rAdcResetPulse] + connect_bd_net -net adc_reset_pulse_r1clk_1 [get_bd_pins adc_reset_pulse_r1clk] [get_bd_pins rf_reset_controller_1/rAdcResetPulse] + connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_r0clk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] [get_bd_pins rf_nco_reset_0/dSysref] connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk] connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1] connect_bd_net -net clock_gates_0_aEnableRf1Bufg2x [get_bd_pins clock_gates_0/aEnableRf1Bufg2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_ce] @@ -1594,7 +1594,8 @@ proc create_hier_cell_rfdc { parentCell nameHier } { connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked] connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_ce] connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg1x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_ce] - connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/rDacResetPulse] [get_bd_pins rf_reset_controller_1/rDacResetPulse] + connect_bd_net -net dac_reset_pulse_r0clk_1 [get_bd_pins dac_reset_pulse_r0clk] [get_bd_pins rf_reset_controller_0/rDacResetPulse] + connect_bd_net -net dac_reset_pulse_r1clk_1 [get_bd_pins dac_reset_pulse_r1clk] [get_bd_pins rf_reset_controller_1/rDacResetPulse] connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins data_clock_mmcm/data_clk] connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins data_clock_mmcm/data_clk_2x] connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked] @@ -1606,7 +1607,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } { connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins radio0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf0_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk] connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks] - connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk] + connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_r0clk] [get_bd_pins capture_sysref/enable_rclk] connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i] connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i] connect_bd_net -net radio1_rfdc_clk_ce_1 [get_bd_pins clock_gates_0/aEnableRf1Bufg1x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_ce] @@ -1651,11 +1652,13 @@ proc create_hier_cell_rfdc { parentCell nameHier } { connect_bd_net -net rf_nco_reset_0_cDac1xNcoUpdateReq [get_bd_pins rf_data_converter/dac1_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateReq] connect_bd_net -net rf_nco_reset_0_cNcoPhaseRst [get_bd_pins rf_data_converter/adc0_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc0_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc1_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc1_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc3_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc3_23_nco_phase_rst] [get_bd_pins rf_data_converter/dac00_nco_phase_rst] [get_bd_pins rf_data_converter/dac01_nco_phase_rst] [get_bd_pins rf_data_converter/dac02_nco_phase_rst] [get_bd_pins rf_data_converter/dac03_nco_phase_rst] [get_bd_pins rf_data_converter/dac10_nco_phase_rst] [get_bd_pins rf_data_converter/dac11_nco_phase_rst] [get_bd_pins rf_data_converter/dac12_nco_phase_rst] [get_bd_pins rf_data_converter/dac13_nco_phase_rst] [get_bd_pins rf_nco_reset_0/cNcoPhaseRst] connect_bd_net -net rf_nco_reset_0_cNcoUpdateEn [get_bd_pins rf_data_converter/adc0_01_nco_update_en] [get_bd_pins rf_data_converter/adc0_23_nco_update_en] [get_bd_pins rf_data_converter/adc1_01_nco_update_en] [get_bd_pins rf_data_converter/adc1_23_nco_update_en] [get_bd_pins rf_data_converter/adc2_01_nco_update_en] [get_bd_pins rf_data_converter/adc2_23_nco_update_en] [get_bd_pins rf_data_converter/adc3_01_nco_update_en] [get_bd_pins rf_data_converter/adc3_23_nco_update_en] [get_bd_pins rf_data_converter/dac00_nco_update_en] [get_bd_pins rf_data_converter/dac01_nco_update_en] [get_bd_pins rf_data_converter/dac02_nco_update_en] [get_bd_pins rf_data_converter/dac03_nco_update_en] [get_bd_pins rf_data_converter/dac10_nco_update_en] [get_bd_pins rf_data_converter/dac11_nco_update_en] [get_bd_pins rf_data_converter/dac12_nco_update_en] [get_bd_pins rf_data_converter/dac13_nco_update_en] [get_bd_pins rf_nco_reset_0/cNcoUpdateEn] - connect_bd_net -net rf_nco_reset_0_dNcoResetDone [get_bd_pins nco_reset_done_dclk] [get_bd_pins rf_nco_reset_0/dNcoResetDone] - connect_bd_net -net rf_reset_controller_0_rAdcRfdcAxiReset_n [get_bd_pins adc_rfdc_axi_resetn_rclk] [get_bd_pins rf_data_converter/m0_axis_aresetn] [get_bd_pins rf_data_converter/m1_axis_aresetn] [get_bd_pins rf_reset_controller_0/rAdcReset_n] + connect_bd_net -net rf_nco_reset_0_dNcoResetDone [get_bd_pins nco_reset_done_r0clk] [get_bd_pins rf_nco_reset_0/dNcoResetDone] + connect_bd_net -net rf_reset_controller_0_rAdcRfdcAxiReset_n [get_bd_pins adc_rfdc_axi_resetn_r0clk] [get_bd_pins rf_data_converter/m0_axis_aresetn] [get_bd_pins rf_data_converter/m1_axis_aresetn] [get_bd_pins rf_reset_controller_0/rAdcReset_n] connect_bd_net -net rf_reset_controller_1_cSoftwareStatus [get_bd_pins reg_rf_reset_control_radio1/gpio2_io_i] [get_bd_pins rf_reset_controller_1/cSoftwareStatus] - connect_bd_net -net rf_reset_controller_1_rAdcReset_n [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_data_converter/m3_axis_aresetn] [get_bd_pins rf_reset_controller_1/rAdcReset_n] - connect_bd_net -net rf_reset_controller_1_rDacReset_n [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_1/rDacReset_n] + connect_bd_net -net rf_reset_controller_1_r2DacReset_n [get_bd_pins dac_data_in_resetn_r1clk2x] [get_bd_pins rf_reset_controller_1/r2DacReset_n] + connect_bd_net -net rf_reset_controller_1_rAdcEnableData [get_bd_pins adc_enable_data_r1clk] [get_bd_pins rf_reset_controller_1/rAdcEnableData] + connect_bd_net -net rf_reset_controller_1_rAdcReset_n [get_bd_pins adc_rfdc_axi_resetn_r1clk] [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_data_converter/m3_axis_aresetn] [get_bd_pins rf_reset_controller_1/rAdcReset_n] + connect_bd_net -net rf_reset_controller_1_rDacReset_n [get_bd_pins dac_data_in_resetn_r1clk] [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_1/rDacReset_n] connect_bd_net -net rf_rfdc_info_sclk_1 [get_bd_pins rf_rfdc_info_sclk] [get_bd_pins reg_rfdc_info/gpio_io_i] connect_bd_net -net rfdc_adc_map_dout [get_bd_pins reg_rfdc_tile_mapping/gpio_io_i] [get_bd_pins rfdc_adc_map/dout] connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq_radio0/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio0/Din] [get_bd_pins slice_iqswap_3_0_radio0/Din] @@ -1665,14 +1668,12 @@ proc create_hier_cell_rfdc { parentCell nameHier } { connect_bd_net -net slice_iqswap_11_8_radio1_Dout [get_bd_pins radio1_invert_dac_iq_r1clk] [get_bd_pins slice_iqswap_11_8_radio1/Dout] connect_bd_net -net slice_iqswap_3_0_radio0_Dout [get_bd_pins radio0_invert_adc_iq_r0clk] [get_bd_pins slice_iqswap_3_0_radio0/Dout] connect_bd_net -net slice_iqswap_3_0_radio1_Dout [get_bd_pins radio1_invert_adc_iq_r1clk] [get_bd_pins slice_iqswap_3_0_radio1/Dout] - connect_bd_net -net start_nco_reset_rclk_1 [get_bd_pins start_nco_reset_dclk] [get_bd_pins rf_nco_reset_0/dStartNcoReset] + connect_bd_net -net start_nco_reset_rclk_1 [get_bd_pins start_nco_reset_r0clk] [get_bd_pins rf_nco_reset_0/dStartNcoReset] connect_bd_net -net sysref_in_0_2 [get_bd_pins sysref_pl_in] [get_bd_pins capture_sysref/sysref_in] connect_bd_net -net x440_rf_reset_contro_0_cSoftwareStatus [get_bd_pins reg_rf_reset_control_radio0/gpio2_io_i] [get_bd_pins rf_reset_controller_0/cSoftwareStatus] - connect_bd_net -net x440_rf_reset_contro_0_r2AdcReset_n [get_bd_pins fir_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2AdcReset_n] - connect_bd_net -net x440_rf_reset_contro_0_r2DacReset_n [get_bd_pins dac_data_in_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2DacReset_n] - connect_bd_net -net x440_rf_reset_contro_0_rAdcEnableData [get_bd_pins adc_enable_data_rclk] [get_bd_pins rf_reset_controller_0/rAdcEnableData] - connect_bd_net -net x440_rf_reset_contro_0_rDacReset_n [get_bd_pins dac_data_in_resetn_rclk] [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacReset_n] - connect_bd_net -net xlconstant_0_dout [get_bd_pins adc_data_out_resetn_dclk] [get_bd_pins dac_data_in_resetn_dclk] [get_bd_pins dac_data_in_resetn_dclk2x] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net x440_rf_reset_contro_0_r2DacReset_n [get_bd_pins dac_data_in_resetn_r0clk2x] [get_bd_pins rf_reset_controller_0/r2DacReset_n] + connect_bd_net -net x440_rf_reset_contro_0_rAdcEnableData [get_bd_pins adc_enable_data_r0clk] [get_bd_pins rf_reset_controller_0/rAdcEnableData] + connect_bd_net -net x440_rf_reset_contro_0_rDacReset_n [get_bd_pins dac_data_in_resetn_r0clk] [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacReset_n] connect_bd_net -net xlconstant_1_dout [get_bd_pins reg_rfdc_tile_mapping/gpio2_io_i] [get_bd_pins rfdc_dac_map/dout] # Restore current instance @@ -3890,13 +3891,12 @@ proc create_root_design { parentCell } { # Create ports - set adc_data_out_resetn_dclk [ create_bd_port -dir O -from 0 -to 0 adc_data_out_resetn_dclk ] - set adc_enable_data_rclk [ create_bd_port -dir O adc_enable_data_rclk ] - set adc_reset_pulse_dclk [ create_bd_port -dir I -type rst adc_reset_pulse_dclk ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $adc_reset_pulse_dclk - set adc_rfdc_axi_resetn_rclk [ create_bd_port -dir O adc_rfdc_axi_resetn_rclk ] + set adc_enable_data_r0clk [ create_bd_port -dir O adc_enable_data_r0clk ] + set adc_enable_data_r1clk [ create_bd_port -dir O adc_enable_data_r1clk ] + set adc_reset_pulse_r0clk [ create_bd_port -dir I adc_reset_pulse_r0clk ] + set adc_reset_pulse_r1clk [ create_bd_port -dir I adc_reset_pulse_r1clk ] + set adc_rfdc_axi_resetn_r0clk [ create_bd_port -dir O adc_rfdc_axi_resetn_r0clk ] + set adc_rfdc_axi_resetn_r1clk [ create_bd_port -dir O adc_rfdc_axi_resetn_r1clk ] set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axis_eth_dma:s_axis_eth_dma:s_axi_hpc1} \ @@ -3910,14 +3910,12 @@ proc create_root_design { parentCell } { ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] set clk_adc0 [ create_bd_port -dir O clk_adc0 ] - set dac_data_in_resetn_dclk [ create_bd_port -dir O -from 0 -to 0 dac_data_in_resetn_dclk ] - set dac_data_in_resetn_dclk2x [ create_bd_port -dir O -from 0 -to 0 dac_data_in_resetn_dclk2x ] - set dac_data_in_resetn_rclk [ create_bd_port -dir O dac_data_in_resetn_rclk ] - set dac_data_in_resetn_rclk2x [ create_bd_port -dir O dac_data_in_resetn_rclk2x ] - set dac_reset_pulse_dclk [ create_bd_port -dir I -type rst dac_reset_pulse_dclk ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $dac_reset_pulse_dclk + set dac_data_in_resetn_r0clk [ create_bd_port -dir O dac_data_in_resetn_r0clk ] + set dac_data_in_resetn_r0clk2x [ create_bd_port -dir O dac_data_in_resetn_r0clk2x ] + set dac_data_in_resetn_r1clk [ create_bd_port -dir O dac_data_in_resetn_r1clk ] + set dac_data_in_resetn_r1clk2x [ create_bd_port -dir O dac_data_in_resetn_r1clk2x ] + set dac_reset_pulse_r0clk [ create_bd_port -dir I dac_reset_pulse_r0clk ] + set dac_reset_pulse_r1clk [ create_bd_port -dir I dac_reset_pulse_r1clk ] set data_clk [ create_bd_port -dir O -type clk data_clk ] set_property -dict [ list \ CONFIG.FREQ_HZ {128000000} \ @@ -3928,8 +3926,7 @@ proc create_root_design { parentCell } { ] $data_clk_2x set data_clock_locked [ create_bd_port -dir O data_clock_locked ] set enable_gated_clocks_clk40 [ create_bd_port -dir I enable_gated_clocks_clk40 ] - set enable_sysref_rclk [ create_bd_port -dir I enable_sysref_rclk ] - set fir_resetn_rclk2x [ create_bd_port -dir O fir_resetn_rclk2x ] + set enable_sysref_r0clk [ create_bd_port -dir I enable_sysref_r0clk ] set gated_base_clks_valid_clk40 [ create_bd_port -dir O gated_base_clks_valid_clk40 ] set irq0_lpd_rpu_n [ create_bd_port -dir I irq0_lpd_rpu_n ] set irq1_lpd_rpu_n [ create_bd_port -dir I irq1_lpd_rpu_n ] @@ -3937,7 +3934,7 @@ proc create_root_design { parentCell } { set jtag0_tdi [ create_bd_port -dir IO jtag0_tdi ] set jtag0_tdo [ create_bd_port -dir I jtag0_tdo ] set jtag0_tms [ create_bd_port -dir IO jtag0_tms ] - set nco_reset_done_dclk [ create_bd_port -dir O nco_reset_done_dclk ] + set nco_reset_done_r0clk [ create_bd_port -dir O nco_reset_done_r0clk ] set pl_clk40 [ create_bd_port -dir O -type clk pl_clk40 ] set pl_clk100 [ create_bd_port -dir O -type clk pl_clk100 ] set pl_clk166 [ create_bd_port -dir O -type clk pl_clk166 ] @@ -3994,9 +3991,9 @@ proc create_root_design { parentCell } { set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {s_axi_hpc0} \ ] $s_axi_hpc0_aclk - set start_nco_reset_dclk [ create_bd_port -dir I start_nco_reset_dclk ] + set start_nco_reset_r0clk [ create_bd_port -dir I start_nco_reset_r0clk ] set sysref_out_pclk [ create_bd_port -dir O sysref_out_pclk ] - set sysref_out_rclk [ create_bd_port -dir O sysref_out_rclk ] + set sysref_out_r0clk [ create_bd_port -dir O sysref_out_r0clk ] set sysref_pl_in [ create_bd_port -dir I sysref_pl_in ] # Create instance: ps @@ -4072,19 +4069,20 @@ proc create_root_design { parentCell } { connect_bd_net -net Net1 [get_bd_ports jtag0_tdi] [get_bd_pins ps/jtag0_tdi] connect_bd_net -net Net2 [get_bd_ports jtag0_tms] [get_bd_pins ps/jtag0_tms] connect_bd_net -net S02_ARESETN_0_1 [get_bd_ports bus_rstn] [get_bd_pins ps/bus_rstn] - connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_ports adc_reset_pulse_dclk] [get_bd_pins rfdc/adc_reset_pulse_dclk] - connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_ports sysref_out_rclk] [get_bd_pins rfdc/sysref_out_rclk] + connect_bd_net -net adc_reset_pulse_r0clk_1 [get_bd_ports adc_reset_pulse_r0clk] [get_bd_pins rfdc/adc_reset_pulse_r0clk] + connect_bd_net -net adc_reset_pulse_r1clk_1 [get_bd_ports adc_reset_pulse_r1clk] [get_bd_pins rfdc/adc_reset_pulse_r1clk] connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_ports sysref_out_pclk] [get_bd_pins rfdc/sysref_out_pclk] connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins ps/clk40] [get_bd_pins rfdc/s_axi_config_clk] connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins ps/clk40_rstn] [get_bd_pins rfdc/s_axi_config_aresetn] connect_bd_net -net clk_in1_0_1 [get_bd_ports pll_ref_clk_in] [get_bd_pins rfdc/pll_ref_clk_in] - connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_ports dac_reset_pulse_dclk] [get_bd_pins rfdc/dac_reset_pulse_dclk] + connect_bd_net -net dac_reset_pulse_r0clk_1 [get_bd_ports dac_reset_pulse_r0clk] [get_bd_pins rfdc/dac_reset_pulse_r0clk] + connect_bd_net -net dac_reset_pulse_r1clk_1 [get_bd_ports dac_reset_pulse_r1clk] [get_bd_pins rfdc/dac_reset_pulse_r1clk] connect_bd_net -net data_clock_mmcm_data_clk [get_bd_ports data_clk] [get_bd_pins rfdc/data_clk] connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_ports data_clk_2x] [get_bd_pins rfdc/data_clk_2x] connect_bd_net -net data_clock_mmcm_locked [get_bd_ports data_clock_locked] [get_bd_pins rfdc/data_clock_locked] connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_ports pll_ref_clk_out] [get_bd_pins rfdc/pll_ref_clk_out] connect_bd_net -net enable_gated_clocks_1 [get_bd_ports enable_gated_clocks_clk40] [get_bd_pins rfdc/enable_gated_clocks_clk40] - connect_bd_net -net enable_rclk_0_1 [get_bd_ports enable_sysref_rclk] [get_bd_pins rfdc/enable_sysref_rclk] + connect_bd_net -net enable_rclk_0_1 [get_bd_ports enable_sysref_r0clk] [get_bd_pins rfdc/enable_sysref_r0clk] connect_bd_net -net gpio2_io_i_0_2 [get_bd_ports rf_dsp_info_clk40] [get_bd_pins rfdc/rf_dsp_info_sclk] connect_bd_net -net gpio_io_i_0_1 [get_bd_ports rf_axi_status_clk40] [get_bd_pins rfdc/rf_axi_status_sclk] connect_bd_net -net inst_zynq_ps_pl_clk0 [get_bd_ports pl_clk100] [get_bd_pins ps/pl_clk100] @@ -4101,20 +4099,20 @@ proc create_root_design { parentCell } { connect_bd_net -net nirq1_lpd_rpu_0_1 [get_bd_ports irq1_lpd_rpu_n] [get_bd_pins ps/irq1_lpd_rpu_n] connect_bd_net -net pl_ps_irq0_1 [get_bd_ports pl_ps_irq0] [get_bd_pins ps/pl_ps_irq0] connect_bd_net -net pl_ps_irq1_0_1 [get_bd_ports pl_ps_irq1] [get_bd_pins ps/pl_ps_irq1_1] - connect_bd_net -net rStartNcoReset_0_1 [get_bd_ports start_nco_reset_dclk] [get_bd_pins rfdc/start_nco_reset_dclk] + connect_bd_net -net rStartNcoReset_0_1 [get_bd_ports start_nco_reset_r0clk] [get_bd_pins rfdc/start_nco_reset_r0clk] connect_bd_net -net rf_data_converter_irq [get_bd_ports rfdc_irq] [get_bd_pins rfdc/rfdc_irq] - connect_bd_net -net rf_nco_reset_0_rNcoResetDone [get_bd_ports nco_reset_done_dclk] [get_bd_pins rfdc/nco_reset_done_dclk] - connect_bd_net -net rf_reset_controller_0_rAdcEnableData [get_bd_ports adc_enable_data_rclk] [get_bd_pins rfdc/adc_enable_data_rclk] + connect_bd_net -net rf_nco_reset_0_rNcoResetDone [get_bd_ports nco_reset_done_r0clk] [get_bd_pins rfdc/nco_reset_done_r0clk] connect_bd_net -net rf_rfdc_info_clk40_1 [get_bd_ports rf_rfdc_info_clk40] [get_bd_pins rfdc/rf_rfdc_info_sclk] - connect_bd_net -net rfdc_adc_rfdc_axi_resetn_rclk [get_bd_ports adc_rfdc_axi_resetn_rclk] [get_bd_pins rfdc/adc_rfdc_axi_resetn_rclk] + connect_bd_net -net rfdc_adc_enable_data_r0clk [get_bd_ports adc_enable_data_r0clk] [get_bd_pins rfdc/adc_enable_data_r0clk] + connect_bd_net -net rfdc_adc_enable_data_r1clk [get_bd_ports adc_enable_data_r1clk] [get_bd_pins rfdc/adc_enable_data_r1clk] + connect_bd_net -net rfdc_adc_rfdc_axi_resetn_r0clk [get_bd_ports adc_rfdc_axi_resetn_r0clk] [get_bd_pins rfdc/adc_rfdc_axi_resetn_r0clk] + connect_bd_net -net rfdc_adc_rfdc_axi_resetn_r1clk [get_bd_ports adc_rfdc_axi_resetn_r1clk] [get_bd_pins rfdc/adc_rfdc_axi_resetn_r1clk] connect_bd_net -net rfdc_clk_adc0 [get_bd_ports clk_adc0] [get_bd_pins rfdc/clk_adc0] - connect_bd_net -net rfdc_d2DacFirReset_n_0 [get_bd_ports dac_data_in_resetn_dclk2x] [get_bd_pins rfdc/dac_data_in_resetn_dclk2x] - connect_bd_net -net rfdc_dAdcDataOutReset_n_0 [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins rfdc/adc_data_out_resetn_dclk] - connect_bd_net -net rfdc_dDacDataInReset_n_0 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins rfdc/dac_data_in_resetn_dclk] - connect_bd_net -net rfdc_dac_data_in_resetn_rclk [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins rfdc/dac_data_in_resetn_rclk] + connect_bd_net -net rfdc_dac_data_in_resetn_r0clk [get_bd_ports dac_data_in_resetn_r0clk] [get_bd_pins rfdc/dac_data_in_resetn_r0clk] + connect_bd_net -net rfdc_dac_data_in_resetn_r0clk2x [get_bd_ports dac_data_in_resetn_r0clk2x] [get_bd_pins rfdc/dac_data_in_resetn_r0clk2x] + connect_bd_net -net rfdc_dac_data_in_resetn_r1clk [get_bd_ports dac_data_in_resetn_r1clk] [get_bd_pins rfdc/dac_data_in_resetn_r1clk] + connect_bd_net -net rfdc_dac_data_in_resetn_r1clk2x [get_bd_ports dac_data_in_resetn_r1clk2x] [get_bd_pins rfdc/dac_data_in_resetn_r1clk2x] connect_bd_net -net rfdc_gated_base_clk_valid [get_bd_ports gated_base_clks_valid_clk40] [get_bd_pins rfdc/gated_base_clks_valid_clk40] - connect_bd_net -net rfdc_r2AdcFirReset_n_0 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins rfdc/fir_resetn_rclk2x] - connect_bd_net -net rfdc_r2DacFirReset_n_0 [get_bd_ports dac_data_in_resetn_rclk2x] [get_bd_pins rfdc/dac_data_in_resetn_rclk2x] connect_bd_net -net rfdc_radio0_invert_adc_iq_r0clk [get_bd_ports radio0_invert_adc_iq_r0clk] [get_bd_pins rfdc/radio0_invert_adc_iq_r0clk] connect_bd_net -net rfdc_radio0_invert_dac_iq_r0clk [get_bd_ports radio0_invert_dac_iq_r0clk] [get_bd_pins rfdc/radio0_invert_dac_iq_r0clk] connect_bd_net -net rfdc_radio1_invert_adc_iq_r1clk [get_bd_ports radio1_invert_adc_iq_r1clk] [get_bd_pins rfdc/radio1_invert_adc_iq_r1clk] @@ -4123,6 +4121,7 @@ proc create_root_design { parentCell } { connect_bd_net -net rfdc_radio1_rfdc_clk_2x [get_bd_ports radio1_rfdc_clk_2x] [get_bd_pins rfdc/radio1_rfdc_clk_2x] connect_bd_net -net rfdc_rfdc_clk [get_bd_ports radio0_rfdc_clk_1x] [get_bd_pins rfdc/radio0_rfdc_clk] connect_bd_net -net rfdc_rfdc_clk_2x [get_bd_ports radio0_rfdc_clk_2x] [get_bd_pins rfdc/radio0_rfdc_clk_2x] + connect_bd_net -net rfdc_sysref_out_r0clk [get_bd_ports sysref_out_r0clk] [get_bd_pins rfdc/sysref_out_r0clk] connect_bd_net -net s_axi_hp0_aclk_1 [get_bd_ports s_axi_hp0_aclk] [get_bd_pins ps/s_axi_hp0_aclk] connect_bd_net -net s_axi_hp1_aclk_1 [get_bd_ports s_axi_hp1_aclk] [get_bd_pins ps/s_axi_hp1_aclk] connect_bd_net -net saxihpc0_fpd_aclk_0_1 [get_bd_ports s_axi_hpc0_aclk] [get_bd_pins ps/s_axi_hpc0_aclk] diff --git a/top/x400/rfdc_timing_control.v b/top/x400/rfdc_timing_control.v index 8cbd475..2eaa91d 100644 --- a/top/x400/rfdc_timing_control.v +++ b/top/x400/rfdc_timing_control.v @@ -22,8 +22,8 @@ module rfdc_timing_control #( parameter NUM_DBOARDS = 2 ) ( // Clocks and resets - input wire clk, - input wire rst, + input wire [ 1*NUM_DBOARDS-1:0] clk, + input wire [ 1*NUM_DBOARDS-1:0] rst, // CtrlPort Slave (from RFNoC Radio Block) input wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_req_wr, @@ -35,18 +35,16 @@ module rfdc_timing_control #( output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data, // RF Reset Control - output reg start_nco_reset, - input wire nco_reset_done, - output reg adc_reset_pulse, - output reg dac_reset_pulse + output reg start_nco_reset, + input wire nco_reset_done, + output reg [ 1*NUM_DBOARDS-1:0] adc_reset_pulse, + output reg [ 1*NUM_DBOARDS-1:0] dac_reset_pulse ); `include "regmap/rfdc_timing_regmap_utils.vh" // Reset registers reg [NUM_DBOARDS-1:0] reg_nco_reset_start = 0; - reg [NUM_DBOARDS-1:0] reg_adc_reset_pulse = 0; - reg [NUM_DBOARDS-1:0] reg_dac_reset_pulse = 0; genvar db; generate @@ -64,6 +62,22 @@ module rfdc_timing_control #( reg [ 31:0] nco_ctrlport_resp_data; wire [ 1:0] nco_ctrlport_resp_status = 2'b0; + wire nco_reset_done_clk; + + // When asserted, nco_reset_done will stay high until the next start_nco_reset + // pulse, which by software design will not happen until this synchronizer + // propagates and the converted nco_reset_done_clk is read. + synchronizer #( + .STAGES (2), + .WIDTH (1), + .INITIAL_VAL (1'h0) + ) synchronizer_nco_reset_done ( + .clk (clk[db]), + .rst (rst[db]), + .in (nco_reset_done), + .out (nco_reset_done_clk) + ); + assign nco_ctrlport_req_wr = s_ctrlport_req_wr [ 1*db+: 1]; assign nco_ctrlport_req_rd = s_ctrlport_req_rd [ 1*db+: 1]; assign nco_ctrlport_req_addr = s_ctrlport_req_addr [20*db+:20]; @@ -77,16 +91,16 @@ module rfdc_timing_control #( // RF Reset Control //----------------------------------------------------------------------- - always @(posedge clk) begin - if (rst) begin + always @(posedge clk[db]) begin + if (rst[db]) begin nco_ctrlport_resp_ack <= 0; reg_nco_reset_start[db] <= 0; nco_ctrlport_resp_data <= 'bX; end else begin // Default assignments reg_nco_reset_start[db] <= 0; - reg_adc_reset_pulse[db] <= 0; - reg_dac_reset_pulse[db] <= 0; + adc_reset_pulse[db] <= 0; + dac_reset_pulse[db] <= 0; nco_ctrlport_resp_ack <= 0; nco_ctrlport_resp_data <= 0; @@ -95,7 +109,7 @@ module rfdc_timing_control #( case (nco_ctrlport_req_addr) NCO_RESET_REG: begin nco_ctrlport_resp_ack <= 1; - nco_ctrlport_resp_data[NCO_RESET_DONE] <= nco_reset_done; + nco_ctrlport_resp_data[NCO_RESET_DONE] <= nco_reset_done_clk; end GEARBOX_RESET_REG: begin nco_ctrlport_resp_ack <= 1; @@ -112,8 +126,8 @@ module rfdc_timing_control #( end GEARBOX_RESET_REG: begin nco_ctrlport_resp_ack <= 1; - reg_adc_reset_pulse[db] <= nco_ctrlport_req_data[ADC_RESET]; - reg_dac_reset_pulse[db] <= nco_ctrlport_req_data[DAC_RESET]; + adc_reset_pulse[db] <= nco_ctrlport_req_data[ADC_RESET]; + dac_reset_pulse[db] <= nco_ctrlport_req_data[DAC_RESET]; end endcase end @@ -125,24 +139,36 @@ module rfdc_timing_control #( //--------------------------------------------------------------------------- - // Merge Resets + // Merge NCO Start //--------------------------------------------------------------------------- // - // There are multiple DBs but only one reset signal for each RF component. - // Since the reset is simply a single cycle pulse, we OR the reset registers - // for each daughter board together. + // There are multiple DBs but only one NCO start pulse, which is expected to + // happen on the clk[0] domain. This pulse will be used to align NCO updates + // to the next SYSREF pulse, which is related to all clk[db] domains. // //--------------------------------------------------------------------------- - always @(posedge clk) begin - if (rst) begin + wire [NUM_DBOARDS-1:0] reg_nco_reset_start_clk0 = 0; + + genvar db_i; + generate + for (db_i = 0; db_i < NUM_DBOARDS; db_i = db_i+1) begin : gen_nco_start_sync + + pulse_synchronizer #( + .MODE("PULSE"), .STAGES(2) + ) pulse_sync_nco_start ( + .clk_a(clk[db_i]), .rst_a(rst[db_i]), .pulse_a(reg_nco_reset_start[db_i]), .busy_a(), + .clk_b(clk[0]), .pulse_b(reg_nco_reset_start_clk0[db_i]) + ); + + end + endgenerate + + always @(posedge clk[0]) begin + if (rst[0]) begin start_nco_reset <= 0; - adc_reset_pulse <= 0; - dac_reset_pulse <= 0; end else begin - start_nco_reset <= |reg_nco_reset_start; - adc_reset_pulse <= |reg_adc_reset_pulse; - dac_reset_pulse <= |reg_dac_reset_pulse; + start_nco_reset <= |reg_nco_reset_start_clk0; end end diff --git a/top/x400/x4xx.v b/top/x400/x4xx.v index 4794447..9b00f1b 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.v @@ -700,14 +700,14 @@ module x4xx ( wire [ 3:0] m_axi_mpm_ep_wstrb; wire [ 0:0] m_axi_mpm_ep_wvalid; - wire adc_data_out_resetn_dclk; - wire adc_enable_data_rclk; - wire adc_rfdc_axi_resetn_rclk; + wire adc_data_out_resetn_dclk; + wire [NUM_TIMEKEEPERS-1:0] adc_enable_data_rclk; + wire [NUM_TIMEKEEPERS-1:0] adc_rfdc_axi_resetn_rclk; - wire dac_data_in_resetn_dclk; - wire dac_data_in_resetn_dclk2x; - wire dac_data_in_resetn_rclk; - wire dac_data_in_resetn_rclk2x; + wire dac_data_in_resetn_dclk; + wire dac_data_in_resetn_dclk2x; + wire [NUM_TIMEKEEPERS-1:0] dac_data_in_resetn_rclk; + wire [NUM_TIMEKEEPERS-1:0] dac_data_in_resetn_rclk2x; wire fir_resetn_rclk2x; @@ -839,10 +839,10 @@ module x4xx ( wire [3:0] eth1_tx_irq; // RF reset control - wire nco_reset_done; - wire start_nco_reset; - wire adc_reset_pulse; - wire dac_reset_pulse; + wire nco_reset_done; + wire start_nco_reset; + wire [NUM_TIMEKEEPERS-1:0] adc_reset_pulse; + wire [NUM_TIMEKEEPERS-1:0] dac_reset_pulse; // Rear panel LEDs control // @@ -1337,25 +1337,27 @@ module x4xx ( ); `elsif X440 x440_ps_rfdc_bd x440_ps_rfdc_bd_i ( - .adc_data_out_resetn_dclk (adc_data_out_resetn_dclk), - .adc_enable_data_rclk (adc_enable_data_rclk), - .adc_reset_pulse_dclk (adc_reset_pulse), - .adc_rfdc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk), + .adc_enable_data_r0clk (adc_enable_data_rclk[0]), + .adc_enable_data_r1clk (adc_enable_data_rclk[1]), + .adc_reset_pulse_r0clk (adc_reset_pulse[0]), + .adc_reset_pulse_r1clk (adc_reset_pulse[1]), + .adc_rfdc_axi_resetn_r0clk (adc_rfdc_axi_resetn_rclk[0]), + .adc_rfdc_axi_resetn_r1clk (adc_rfdc_axi_resetn_rclk[1]), .bus_clk (bus_clk), .bus_rstn (bus_clk_rstn), .clk40 (clk40), .clk40_rstn (clk40_rstn), - .dac_data_in_resetn_dclk (dac_data_in_resetn_dclk), - .dac_data_in_resetn_dclk2x (dac_data_in_resetn_dclk2x), - .dac_data_in_resetn_rclk (dac_data_in_resetn_rclk), - .dac_data_in_resetn_rclk2x (dac_data_in_resetn_rclk2x), - .dac_reset_pulse_dclk (dac_reset_pulse), + .dac_data_in_resetn_r0clk (dac_data_in_resetn_rclk[0]), + .dac_data_in_resetn_r1clk (dac_data_in_resetn_rclk[1]), + .dac_data_in_resetn_r0clk2x (dac_data_in_resetn_rclk2x[0]), + .dac_data_in_resetn_r1clk2x (dac_data_in_resetn_rclk2x[1]), + .dac_reset_pulse_r0clk (dac_reset_pulse[0]), + .dac_reset_pulse_r1clk (dac_reset_pulse[1]), .data_clk (data_clk), .data_clk_2x (data_clk_2x), .data_clock_locked (), .enable_gated_clocks_clk40 (1'b1), - .enable_sysref_rclk (1'b1), - .fir_resetn_rclk2x (fir_resetn_rclk2x), + .enable_sysref_r0clk (1'b1), .gated_base_clks_valid_clk40 (), .radio0_invert_adc_iq_r0clk (invert_adc_iq_rclk2[3:0]), .radio0_invert_dac_iq_r0clk (invert_dac_iq_rclk2[3:0]), @@ -1367,7 +1369,7 @@ module x4xx ( .jtag0_tdi (), .jtag0_tdo (), .jtag0_tms (), - .nco_reset_done_dclk (nco_reset_done), + .nco_reset_done_r0clk (nco_reset_done), .pl_clk40 (clk40), .pl_clk100 (clk100), .pl_clk166 (clk166), @@ -1391,9 +1393,9 @@ module x4xx ( .s_axi_hp0_aclk (clk40), .s_axi_hp1_aclk (clk40), .s_axi_hpc0_aclk (), - .start_nco_reset_dclk (start_nco_reset), + .start_nco_reset_r0clk (start_nco_reset), .sysref_out_pclk (), - .sysref_out_rclk (), + .sysref_out_r0clk (), .sysref_pl_in (sysref_pl), `ifdef QSFP0_0 .s_axi_hp0_aruser (axi_hp0_aruser), @@ -2212,8 +2214,8 @@ module x4xx ( .dsp_info_sclk (rf_dsp_info_clk40[10*db_i+:10]), .rfdc_info_sclk (rf_rfdc_info_clk40[16*db_i+:16]), .axi_status_sclk (rf_axi_status_clk40[16*db_i +: 16]), - .adc_enable_data_rclk (adc_enable_data_rclk), - .adc_rfdc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk), + .adc_enable_data_rclk (adc_enable_data_rclk[db_i]), + .adc_rfdc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk[db_i]), .version_info (rf_core_version[db_i]) ); end // gen_rf_core_full diff --git a/top/x400/x4xx_core.v b/top/x400/x4xx_core.v index 67f5761..ad8dc50 100644 --- a/top/x400/x4xx_core.v +++ b/top/x400/x4xx_core.v @@ -208,10 +208,10 @@ module x4xx_core #( input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_data, // RF Reset Control - output wire start_nco_reset, - input wire nco_reset_done, - output wire adc_reset_pulse, - output wire dac_reset_pulse, + output wire start_nco_reset, + input wire nco_reset_done, + output wire [NUM_TIMEKEEPERS-1:0] adc_reset_pulse, + output wire [NUM_TIMEKEEPERS-1:0] dac_reset_pulse, // Version (Constant) // Each component consists of a 96-bit vector (refer to versioning_utils.vh) diff --git a/top/x400/x4xx_core_common.v b/top/x400/x4xx_core_common.v index 4646c59..7f7fc58 100644 --- a/top/x400/x4xx_core_common.v +++ b/top/x400/x4xx_core_common.v @@ -37,7 +37,7 @@ module x4xx_core_common #( parameter RFNOC_PROTOVER = {8'd1, 8'd0}, parameter NUM_DBOARDS = 2, parameter NUM_CH_PER_DB = 2, - parameter NUM_TIMEKEEPERS = NUM_DBOARDS, + parameter NUM_TIMEKEEPERS = NUM_DBOARDS, parameter PCIE_PRESENT = 0 ) ( // Clocks and resets @@ -134,10 +134,10 @@ module x4xx_core_common #( input wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_data, // RF Reset Control - output wire start_nco_reset, - input wire nco_reset_done, - output wire adc_reset_pulse, - output wire dac_reset_pulse, + output wire start_nco_reset, + input wire nco_reset_done, + output wire [NUM_TIMEKEEPERS-1:0] adc_reset_pulse, + output wire [NUM_TIMEKEEPERS-1:0] dac_reset_pulse, // Radio state for ATR control input wire [NUM_DBOARDS*NUM_CH_PER_DB-1:0] tx_running, @@ -596,6 +596,60 @@ module x4xx_core_common #( end endgenerate + // Synchronize DB1 ctrlport to radio_clk[0] domain + wire radio1_crossed_req_wr; + wire radio1_crossed_req_rd; + wire [ 19:0] radio1_crossed_req_addr; + wire [ 31:0] radio1_crossed_req_data; + wire radio1_crossed_resp_ack; + wire [ 1:0] radio1_crossed_resp_status; + wire [ 31:0] radio1_crossed_resp_data; + + generate + // Crossing only necessary if there are multiple timekeepers/radio rates. + if (NUM_TIMEKEEPERS > 1) begin : gen_ctrlport_dio_clk_cross + ctrlport_clk_cross ctrlport_clk_radio_dio ( + .rst (radio_rst[1]), + .s_ctrlport_clk (radio_clk[1]), + .s_ctrlport_req_wr (radio_dio_req_wr[1*1 +: 1]), + .s_ctrlport_req_rd (radio_dio_req_rd[1*1 +: 1]), + .s_ctrlport_req_addr (radio_dio_req_addr[1*20 +: 20]), + .s_ctrlport_req_portid (10'b0), + .s_ctrlport_req_rem_epid (16'b0), + .s_ctrlport_req_rem_portid (10'b0), + .s_ctrlport_req_data (radio_dio_req_data[1*32 +: 32]), + .s_ctrlport_req_byte_en (4'hF), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), + .s_ctrlport_resp_ack (radio_dio_resp_ack[1*1 +: 1]), + .s_ctrlport_resp_status (radio_dio_resp_status[1*2 +: 2]), + .s_ctrlport_resp_data (radio_dio_resp_data[1*32 +: 32]), + .m_ctrlport_clk (radio_clk[0]), + .m_ctrlport_req_wr (radio1_crossed_req_wr), + .m_ctrlport_req_rd (radio1_crossed_req_rd), + .m_ctrlport_req_addr (radio1_crossed_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (radio1_crossed_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (radio1_crossed_resp_ack), + .m_ctrlport_resp_status (radio1_crossed_resp_status), + .m_ctrlport_resp_data (radio1_crossed_resp_data) + ); + end else begin + assign radio1_crossed_req_wr = radio_dio_req_wr[1*1 +: 1]; + assign radio1_crossed_req_rd = radio_dio_req_rd[1*1 +: 1]; + assign radio1_crossed_req_addr = radio_dio_req_addr[1*20 +: 20]; + assign radio1_crossed_req_data = radio_dio_req_data[1*32 +: 32]; + assign radio_dio_resp_ack[1*1 +: 1] = radio1_crossed_resp_ack; + assign radio_dio_resp_status[1*2 +: 2] = radio1_crossed_resp_status; + assign radio_dio_resp_data[1*32 +: 32] = radio1_crossed_resp_data; + end + endgenerate + //------------------------------------------------------------------------- // RF Timing Reset Control @@ -604,8 +658,8 @@ module x4xx_core_common #( rfdc_timing_control #( .NUM_DBOARDS (NUM_DBOARDS) ) rfdc_timing_control_i ( - .clk (radio_clk[0]), - .rst (radio_rst[0]), + .clk (radio_clk), + .rst (radio_rst), .s_ctrlport_req_wr (rf_ctrlport_req_wr), .s_ctrlport_req_rd (rf_ctrlport_req_rd), .s_ctrlport_req_addr (rf_ctrlport_req_addr), @@ -750,19 +804,19 @@ module x4xx_core_common #( ) ctrlport_combiner_dio ( .ctrlport_clk (radio_clk[0]), .ctrlport_rst (radio_rst[0]), - .s_ctrlport_req_wr ({radio_dio_req_wr, windowed_mpm_dio_req_wr}), - .s_ctrlport_req_rd ({radio_dio_req_rd, windowed_mpm_dio_req_rd}), - .s_ctrlport_req_addr ({radio_dio_req_addr, windowed_mpm_dio_req_addr}), + .s_ctrlport_req_wr ({radio1_crossed_req_wr, radio_dio_req_wr[0*1 +: 1], windowed_mpm_dio_req_wr}), + .s_ctrlport_req_rd ({radio1_crossed_req_rd, radio_dio_req_rd[0*1 +: 1], windowed_mpm_dio_req_rd}), + .s_ctrlport_req_addr ({radio1_crossed_req_addr, radio_dio_req_addr[0*20 +: 20], windowed_mpm_dio_req_addr}), .s_ctrlport_req_portid ({(NUM_DBOARDS+1){10'b0}}), .s_ctrlport_req_rem_epid ({(NUM_DBOARDS+1){16'b0}}), .s_ctrlport_req_rem_portid ({(NUM_DBOARDS+1){10'b0}}), - .s_ctrlport_req_data ({radio_dio_req_data, windowed_mpm_dio_req_data}), + .s_ctrlport_req_data ({radio1_crossed_req_data, radio_dio_req_data[0*32 +: 32], windowed_mpm_dio_req_data}), .s_ctrlport_req_byte_en ({(NUM_DBOARDS+1){4'hF}}), .s_ctrlport_req_has_time ({(NUM_DBOARDS+1){1'b0}}), .s_ctrlport_req_time ({(NUM_DBOARDS+1){64'b0}}), - .s_ctrlport_resp_ack ({radio_dio_resp_ack, windowed_mpm_dio_resp_ack}), - .s_ctrlport_resp_status ({radio_dio_resp_status, windowed_mpm_dio_resp_status}), - .s_ctrlport_resp_data ({radio_dio_resp_data, windowed_mpm_dio_resp_data}), + .s_ctrlport_resp_ack ({radio1_crossed_resp_ack, radio_dio_resp_ack[0*1 +: 1], windowed_mpm_dio_resp_ack}), + .s_ctrlport_resp_status ({radio1_crossed_resp_status, radio_dio_resp_status[0*2 +: 2], windowed_mpm_dio_resp_status}), + .s_ctrlport_resp_data ({radio1_crossed_resp_data, radio_dio_resp_data[0*32 +: 32], windowed_mpm_dio_resp_data}), .m_ctrlport_req_wr (dio_ctrlport_req_wr), .m_ctrlport_req_rd (dio_ctrlport_req_rd), .m_ctrlport_req_addr (dio_ctrlport_req_addr),