From dd683cdee373eb0537395e783ad2dc9e79b776dc Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 9 Feb 2023 13:03:04 -0600 Subject: [PATCH] fpga: rfnoc: Add DEVICE_FAMILY to stream endpoint Original-commit: 914a2b08f77a1725bf74a2cccf09b49f7506f53d --- lib/rfnoc/core/chdr_stream_endpoint.v | 5 ++++- lib/rfnoc/core/chdr_stream_input.v | 4 +++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/rfnoc/core/chdr_stream_endpoint.v b/lib/rfnoc/core/chdr_stream_endpoint.v index e37b9a9..e0e667e 100644 --- a/lib/rfnoc/core/chdr_stream_endpoint.v +++ b/lib/rfnoc/core/chdr_stream_endpoint.v @@ -8,11 +8,12 @@ // The implementation of a stream endpoint. This module serves as // an endpoint for a bidirectional stream. It implement a control // and a data path, both of which can be individually enabled using -// parameters. The control path contains a bidirectional CHDR to +// parameters. The control path contains a bidirectional CHDR to // AXIS-Control converter. The data path has a stream input and // output port. // // Parameters: +// - DEVICE_FAMILY: The FPGA device family (e.g., "7SERIES" or "ULTRASCALE") // - PROTOVER: RFNoC protocol version {8'd, 8'd} // - CHDR_W: Width of the CHDR bus in bits // - INST_NUM: The instance number of this module @@ -37,6 +38,7 @@ // - signal_*_err : Notify upstream that we encountered an error module chdr_stream_endpoint #( + parameter DEVICE_FAMILY = "7SERIES", parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter CHDR_W = 64, parameter [9:0] INST_NUM = 0, @@ -491,6 +493,7 @@ module chdr_stream_endpoint #( // Stream endpoint flow-control input module chdr_stream_input #( + .DEVICE_FAMILY(DEVICE_FAMILY), .CHDR_W(CHDR_W), .BUFF_SIZE(INGRESS_BUFF_SIZE), .FLUSH_TIMEOUT_W(INPUT_FLUSH_TIMEOUT_W), .MONITOR_EN(0), .SIGNAL_ERRS(REPORT_STRM_ERRS) diff --git a/lib/rfnoc/core/chdr_stream_input.v b/lib/rfnoc/core/chdr_stream_input.v index 0f5ec89..93acf85 100644 --- a/lib/rfnoc/core/chdr_stream_input.v +++ b/lib/rfnoc/core/chdr_stream_input.v @@ -13,6 +13,7 @@ // using stream command packets. // // Parameters: +// - DEVICE_FAMILY: The FPGA device family (e.g., "7SERIES" or "ULTRASCALE") // - CHDR_W: Width of the CHDR bus in bits // - BUFF_SIZE: Buffer size in log2 of the number of words in the // ingress buffer for the stream @@ -29,6 +30,7 @@ // module chdr_stream_input #( + parameter DEVICE_FAMILY = "7SERIES", parameter CHDR_W = 256, parameter BUFF_SIZE = 14, parameter FLUSH_TIMEOUT_W = 14, @@ -77,7 +79,7 @@ module chdr_stream_input #( wire [15:0] buff_info; chdr_ingress_fifo #( - .WIDTH(CHDR_W), .SIZE(BUFF_SIZE) + .DEVICE(DEVICE_FAMILY), .WIDTH(CHDR_W), .SIZE(BUFF_SIZE) ) ingress_fifo_i ( .clk(clk), .reset(rst), .clear(1'b0), .i_tdata(s_axis_chdr_tdata), .i_tlast(s_axis_chdr_tlast),