fpga: rfnoc: fft: Add FFT packetize modules

Original-commit: 97ea89fac5c1889e5c0da44349d5f4be3d788965

lib/rfnoc/blocks/rfnoc_block_fft/fft_packetize_tb/Makefile

@@ -0,0 +1,53 @@
+#
+# Copyright 2025 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+#-------------------------------------------------
+# Top-of-Makefile
+#-------------------------------------------------
+# Define BASE_DIR to point to the "top" dir
+BASE_DIR = $(abspath ../../../../../top)
+# Include viv_sim_preample after defining BASE_DIR
+include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
+
+#-------------------------------------------------
+# IP Specific
+#-------------------------------------------------
+# If simulation contains IP, define the IP_DIR and point
+# it to the base level IP directory
+LIB_IP_DIR = $(BASE_DIR)/../lib/ip
+
+#-------------------------------------------------
+# Design Specific
+#-------------------------------------------------
+# Include makefiles and sources for the DUT and its
+# dependencies.
+include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
+include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
+include $(BASE_DIR)/../lib/axi/Makefile.srcs
+include Makefile.srcs
+
+DESIGN_SRCS += $(abspath \
+$(RFNOC_CORE_SRCS) \
+$(RFNOC_UTIL_SRCS) \
+$(FFT_REORDER_SRCS) \
+)
+
+#-------------------------------------------------
+# Testbench Specific
+#-------------------------------------------------
+SIM_TOP = fft_packetize_all_tb
+SIM_SRCS = $(abspath \
+fft_packetize_tb.sv \
+fft_packetize_all_tb.sv \
+)
+
+#-------------------------------------------------
+# Bottom-of-Makefile
+#-------------------------------------------------
+# Include all simulator specific makefiles here
+# Each should define a unique target to simulate
+# e.g. xsim, vsim, etc and a common "clean" target
+include $(BASE_DIR)/../tools/make/viv_simulator.mak

lib/rfnoc/blocks/rfnoc_block_fft/fft_packetize_tb/Makefile.srcs

@@ -0,0 +1,11 @@
+#
+# Copyright 2025 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+FFT_REORDER_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_fft/, \
+fft_packetize_pkg.sv \
+fft_packetize.sv \
+fft_depacketize.sv \
+))

lib/rfnoc/blocks/rfnoc_block_fft/fft_packetize_tb/fft_packetize_all_tb.sv

@@ -0,0 +1,44 @@
+//
+// Copyright 2025 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: fft_packetize_all_tb
+//
+// Description:
+//
+//   Top-level testbench for fft_packetize_tb, testing different configurations
+//   of the module.
+//
+
+module fft_packetize_all_tb;
+
+  // Parameters:
+  //                 ┌ NIPC
+  //                 |  ┌ NUM_CHAN
+  //                 |  |  ┌ EN_CP_REMOVAL
+  //                 |  |  |  ┌ EN_CP_INSERTION
+  //                 |  |  |  |  ┌ EN_DATA_FIFOS
+  //                 |  |  |  |  |  ┌ EN_TIME_ALL_PKTS
+  //                 |  |  |  |  |  |
+  //                 |  |  |  |  |  |
+  //                 |  |  |  |  |  |
+  fft_packetize_tb #(1, 1, 0, 0, 0, 0) tb_01();
+  fft_packetize_tb #(1, 2, 0, 1, 0, 0) tb_02();
+  fft_packetize_tb #(1, 3, 1, 0, 0, 0) tb_03();
+  fft_packetize_tb #(1, 1, 1, 1, 0, 0) tb_04();
+  fft_packetize_tb #(1, 2, 1, 1, 1, 1) tb_05();
+
+  fft_packetize_tb #(2, 2, 0, 0, 0, 0) tb_11();
+  fft_packetize_tb #(2, 1, 0, 1, 0, 0) tb_12();
+  fft_packetize_tb #(2, 2, 1, 0, 0, 0) tb_13();
+  fft_packetize_tb #(2, 3, 1, 1, 0, 0) tb_14();
+  fft_packetize_tb #(2, 1, 1, 1, 1, 1) tb_15();
+
+  fft_packetize_tb #(4, 1, 0, 0, 0, 0) tb_21();
+  fft_packetize_tb #(4, 2, 0, 1, 0, 0) tb_22();
+  fft_packetize_tb #(4, 1, 1, 0, 0, 0) tb_23();
+  fft_packetize_tb #(4, 2, 1, 1, 0, 0) tb_24();
+  fft_packetize_tb #(4, 3, 1, 1, 1, 1) tb_25();
+
+endmodule : fft_packetize_all_tb