From d006250dc1939a5a08be877be99e8d49547c8f4c Mon Sep 17 00:00:00 2001 From: Jonathon Pendlum Date: Tue, 2 Jan 2024 13:21:56 -0500 Subject: [PATCH] fpga: x400: Add PPS interface to X410/X440 BSP This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`) for X440 which allows modules inside the RFNoC image core to access the FPGA. Note that accessing the PPS signal is generally not required for RFNoC blocks which require access to timing. Co-authored-by: Martin Braun Original-commit: c3525362643b56910692ad8ddc5d0e8cedd1869c --- top/x400/x4xx_core.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/top/x400/x4xx_core.v b/top/x400/x4xx_core.v index 85e0c48..fba2f3d 100644 --- a/top/x400/x4xx_core.v +++ b/top/x400/x4xx_core.v @@ -848,8 +848,11 @@ module x4xx_core #( `ifdef X440 .radio_time0 (radio_time[0*64+:64]), .radio_time1 (radio_time[1*64+:64]), + .pps0 (pps_radioclk[0] ), + .pps1 (pps_radioclk[1] ), `else .radio_time (radio_time[0*64+:64]), + .pps (pps_radioclk[0] ), `endif .dram0_axi_rst (dram_rst), .dram0_m_axi_awid (dram0_axi_awid),