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fpga: lib: Fix axis_strm_monitor parameters

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Original-commit: a51ccbba88d6a3f3012b84a1eed55725d41c7fd7
This commit is contained in:
Wade Fife
2020-10-20 21:10:16 -05:00
parent e41c34776c
commit cc5c306897
1 changed files with 2 additions and 2 deletions
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lib/fifo/axis_strm_monitor.v
+2 -2
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@@ -57,7 +57,7 @@ module axis_strm_monitor #(
end end
end end
generate if (PKT_LENGTH_EN == 0) begin generate if (PKT_LENGTH_EN) begin
// Count the number of lines (transfers) in a packet // Count the number of lines (transfers) in a packet
always @(posedge clk) begin always @(posedge clk) begin
if (reset | eop) begin if (reset | eop) begin
@@ -71,7 +71,7 @@ module axis_strm_monitor #(
always @(*) pkt_length <= 16'd0; always @(*) pkt_length <= 16'd0;
end endgenerate end endgenerate
generate if (PKT_LENGTH_EN == 0) begin generate if (PKT_CHKSUM_EN) begin
// Compute the XOR checksum of the lines in a packet // Compute the XOR checksum of the lines in a packet
reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}}; reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}};
always @(posedge clk) begin always @(posedge clk) begin