fpga: Add license checker module
Original-commit: 8ed8927b944e7ad8a5da040c7f1951aad3535e11
This commit is contained in:
Martin Braun
@@ -0,0 +1,45 @@
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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DESIGN_SRCS += \
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$(abspath ../../../sec/license_check.sv) \
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$(abspath ../../../sec/sha256.v) \
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$(abspath ../../../sec/sha256_core.v) \
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$(abspath ../../../sec/sha256_k_constants.v) \
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$(abspath ../../../sec/sha256_stream.v) \
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$(abspath ../../../sec/sha256_w_mem.v) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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MODELSIM_ARGS += glbl
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = license_check_tb
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SIM_SRCS = \
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$(abspath license_check_tb.sv) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,38 @@
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Calculate hash values for license_check_tb
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"""
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import hashlib
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serial = [0x01, 0x23, 0x45, 0x67, 0x8A, 0xBC, 0xDE, 0xF0, 0x0C, 0x0D, 0xE0, 0xBB]
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pkey = [0x00] * 37 + [0x05, 0xEC]
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feature0 = [0x00, 0x00, 0xC0, 0xDE]
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feature1 = [0x00, 0x00, 0xF0, 0x0D]
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def main():
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"""
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Calc and print hashes
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"""
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sha0 = hashlib.sha256()
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sha0.update(bytes(serial + pkey + feature0))
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hash0 = sha0.hexdigest()
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sha1 = hashlib.sha256()
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sha1.update(bytes(serial + pkey + feature1))
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hash1 = sha1.hexdigest()
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print(f"// Feature 0 hash: 256'h{hash0}")
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hash0_words = [f"hash0_{int(i/8)} = 32'h" + hash0[i:i+8] for i in range(0, 64, 8)]
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print("// Individual words:")
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print(";\n localparam ".join(hash0_words))
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print(f"// Feature 1 hash: 256'h{hash1}")
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hash1_words = [f"hash1_{int(i/8)} = 32'h" + hash1[i:i+8] for i in range(0, 64, 8)]
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print("// Individual words:")
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print(";\n localparam ".join(hash1_words))
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if __name__ == "__main__":
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main()
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@@ -0,0 +1,292 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description:
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//
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// Testbench for license_check and the sha256 module
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//
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`default_nettype none
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module license_check_tb ();
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// Include macros and time declarations for use with PkgTestExec
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`include "test_exec.svh"
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import PkgTestExec::*;
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localparam real CLK_PERIOD = 10.0; // ns
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localparam [95:0] SERIAL = 96'h012345678ABCDEF00C0DE0BB;
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localparam int PKEY_W = 312;
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localparam [PKEY_W-1:0] PRIVATE_KEY = 312'h5EC;
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localparam int FEATURE0 = 32'hC0DE;
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localparam int FEATURE1 = 32'hF00D;
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localparam FEATURE_ADDR = 0;
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localparam KEY_ADDR = 4;
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localparam RB_ADDR = 8;
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// Note: hashes are calculated with gen_sha256.py
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// Feature 0 hash: 256'h80f122aad504a1ec7ae8f37b4eee414cf1cf32ecc543ee2e1d4e1d4ae59eb41b
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// Individual words:
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localparam hash0_0 = 32'h80f122aa;
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localparam hash0_1 = 32'hd504a1ec;
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localparam hash0_2 = 32'h7ae8f37b;
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localparam hash0_3 = 32'h4eee414c;
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localparam hash0_4 = 32'hf1cf32ec;
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localparam hash0_5 = 32'hc543ee2e;
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localparam hash0_6 = 32'h1d4e1d4a;
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localparam hash0_7 = 32'he59eb41b;
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// Feature 1 hash: 256'hefd81f78a5fdee0a16ed039cfa51db769a8da088328f8ed73d6af85ba1ce57d4
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// Individual words:
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localparam hash1_0 = 32'hefd81f78;
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localparam hash1_1 = 32'ha5fdee0a;
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localparam hash1_2 = 32'h16ed039c;
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localparam hash1_3 = 32'hfa51db76;
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localparam hash1_4 = 32'h9a8da088;
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localparam hash1_5 = 32'h328f8ed7;
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localparam hash1_6 = 32'h3d6af85b;
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localparam hash1_7 = 32'ha1ce57d4;
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//---------------------------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------------------------
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bit clk;
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bit rst;
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bit rst_dut = 0;
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sim_clock_gen #(.PERIOD(CLK_PERIOD))
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clk_gen (.clk(clk), .rst(rst));
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//---------------------------------------------------------------------------
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// Device Under Test (DUT)
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//---------------------------------------------------------------------------
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logic i_ctrlport_req_rd = 1'b0;
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logic i_ctrlport_req_wr = 1'b0;
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logic [19:0] i_ctrlport_req_addr = 20'h0;
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logic [31:0] i_ctrlport_req_data = 32'h0;
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logic o_ctrlport_resp_ack;
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logic [1:0] o_ctrlport_resp_status;
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logic [31:0] o_ctrlport_resp_data;
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logic [1:0] feature_enabled;
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license_check #(
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.BASE_ADDR (0),
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.PKEY_W (PKEY_W),
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.SERIAL_W (96),
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.NUM_FEATURES (2),
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.FEATURE_IDS ({FEATURE1, FEATURE0}),
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.PRIVATE_KEY (PRIVATE_KEY)
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) license_check_dut (
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.clk(clk),
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.rst(rst | rst_dut),
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.serial(SERIAL),
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.s_ctrlport_req_wr (i_ctrlport_req_wr),
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.s_ctrlport_req_rd (i_ctrlport_req_rd),
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.s_ctrlport_req_addr (i_ctrlport_req_addr),
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.s_ctrlport_req_data (i_ctrlport_req_data),
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.s_ctrlport_resp_ack (o_ctrlport_resp_ack),
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.s_ctrlport_resp_status (o_ctrlport_resp_status),
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.s_ctrlport_resp_data (o_ctrlport_resp_data),
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.feature_enabled(feature_enabled)
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);
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//--------------------------------
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// Tasks
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//--------------------------------
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// Write a data word via ctrlport transaction. Will run into timeout if no
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// ACK is returned.
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task automatic ctrlport_poke32(int addr, int data);
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i_ctrlport_req_addr <= addr;
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i_ctrlport_req_data <= data;
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i_ctrlport_req_wr <= 1'b1;
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@(posedge clk);
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i_ctrlport_req_wr <= 1'b0;
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while (!o_ctrlport_resp_ack) @(posedge clk);
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test.assert_error(
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!o_ctrlport_resp_status,
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$sformatf("CtrlPort write response status not zero (%d)!",
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o_ctrlport_resp_status));
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endtask
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task automatic ctrlport_poke32_status(int addr, int data, int exp_status);
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i_ctrlport_req_addr <= addr;
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i_ctrlport_req_data <= data;
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i_ctrlport_req_wr <= 1'b1;
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@(posedge clk);
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i_ctrlport_req_wr <= 1'b0;
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while (!o_ctrlport_resp_ack) @(posedge clk);
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test.assert_error(
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o_ctrlport_resp_status == exp_status,
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$sformatf("CtrlPort write response status not %d (%d)!",
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exp_status, o_ctrlport_resp_status));
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endtask
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task automatic ctrlport_peek32(int addr, int expected_data);
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i_ctrlport_req_addr <= addr;
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i_ctrlport_req_rd <= 1'b1;
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@(posedge clk);
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i_ctrlport_req_rd <= 1'b0;
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while (!o_ctrlport_resp_ack) @(posedge clk);
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test.assert_error(
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!o_ctrlport_resp_status,
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$sformatf("CtrlPort read response status not zero (%d)!",
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o_ctrlport_resp_status));
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test.assert_error(
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o_ctrlport_resp_data == expected_data,
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$sformatf("Incorrect peek value: %x! Expected %x.",
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o_ctrlport_resp_data, expected_data));
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endtask
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//---------------------------------------------------------------------------
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// Main Test Process
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//---------------------------------------------------------------------------
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initial begin : tb_main
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string tb_name;
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tb_name = $sformatf("device_dna_ctrlport");
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test.start_tb(tb_name, 10ms);
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//-------------------------------------------------------
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// Reset clock generator and wait for reset to complete
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//-------------------------------------------------------
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test.start_test("Reset", 100us);
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clk_gen.reset();
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if (rst) @rst;
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test.end_test();
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//--------------------------------
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// Test Sequences
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//--------------------------------
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// Verify that all features are disabled after reset
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test.start_test("Checking reset state", 2us);
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test.assert_error(
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feature_enabled == 0,
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$sformatf("Features enabled after reset: %x", feature_enabled));
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ctrlport_peek32(RB_ADDR, 32'b00000000000000000000000000000000);
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test.end_test();
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/// Regular feature unlock
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test.start_test("Checking feature 0 unlock", 100us);
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ctrlport_poke32(FEATURE_ADDR, FEATURE0);
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ctrlport_poke32(KEY_ADDR, hash0_0);
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ctrlport_poke32(KEY_ADDR, hash0_1);
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ctrlport_poke32(KEY_ADDR, hash0_2);
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ctrlport_poke32(KEY_ADDR, hash0_3);
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ctrlport_poke32(KEY_ADDR, hash0_4);
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ctrlport_poke32(KEY_ADDR, hash0_5);
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ctrlport_poke32(KEY_ADDR, hash0_6);
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ctrlport_poke32(KEY_ADDR, hash0_7);
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test.assert_error(feature_enabled == 2'b1,
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$sformatf("Feature enable is not 1 (%x)", feature_enabled));
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ctrlport_peek32(RB_ADDR, 32'b10000000000000000000000000000000);
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test.end_test();
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test.start_test("Checking feature 1 unlock", 100us);
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ctrlport_poke32(FEATURE_ADDR, FEATURE1);
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ctrlport_poke32(KEY_ADDR, hash1_0);
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ctrlport_poke32(KEY_ADDR, hash1_1);
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ctrlport_poke32(KEY_ADDR, hash1_2);
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ctrlport_poke32(KEY_ADDR, hash1_3);
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ctrlport_poke32(KEY_ADDR, hash1_4);
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ctrlport_poke32(KEY_ADDR, hash1_5);
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ctrlport_poke32(KEY_ADDR, hash1_6);
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ctrlport_poke32(KEY_ADDR, hash1_7);
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test.assert_error(feature_enabled == 2'b11,
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$sformatf("Feature enable is not 0b11 (%x)", feature_enabled));
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ctrlport_peek32(RB_ADDR, 32'b10000000000000000000000000000001);
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test.end_test();
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/// Reset and make sure features are no longer enabled
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test.start_test("Testing reset after unlock", 100us);
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rst_dut <= 1;
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@(posedge clk);
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rst_dut <= 0;
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@(posedge clk);
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test.assert_error(feature_enabled == 2'b00,
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$sformatf("Feature enable is not 0b00 (%x)", feature_enabled));
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ctrlport_peek32(RB_ADDR, 32'h0);
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test.end_test();
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/// Writing a hash value now is invalid
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test.start_test("Checking error case: No FID loaded", 100us);
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ctrlport_poke32_status(KEY_ADDR, 32'h1234ABCD, 2'b1);
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test.end_test();
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/// Try uploading invalid key
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test.start_test("Checking feature 0 unlock with invalid key", 100us);
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ctrlport_poke32(FEATURE_ADDR, FEATURE0);
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ctrlport_poke32(KEY_ADDR, hash0_0);
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ctrlport_poke32(KEY_ADDR, hash0_1);
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ctrlport_poke32(KEY_ADDR, hash0_2);
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ctrlport_poke32(KEY_ADDR, hash0_3);
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ctrlport_poke32(KEY_ADDR, hash0_4);
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ctrlport_poke32(KEY_ADDR, hash0_5);
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ctrlport_poke32(KEY_ADDR, hash0_6);
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ctrlport_poke32(KEY_ADDR, 32'h0);
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test.assert_error(feature_enabled == 2'b0,
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$sformatf("Feature enable is not 0 (%x)", feature_enabled));
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test.end_test();
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/// Now again valid key after failure
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test.start_test("Checking feature 0 unlock with valid key again after fail", 100us);
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ctrlport_poke32(FEATURE_ADDR, FEATURE0);
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ctrlport_poke32(KEY_ADDR, hash0_0);
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ctrlport_poke32(KEY_ADDR, hash0_1);
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ctrlport_poke32(KEY_ADDR, hash0_2);
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ctrlport_poke32(KEY_ADDR, hash0_3);
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ctrlport_poke32(KEY_ADDR, hash0_4);
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ctrlport_poke32(KEY_ADDR, hash0_5);
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ctrlport_poke32(KEY_ADDR, hash0_6);
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ctrlport_poke32(KEY_ADDR, hash0_7);
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test.assert_error(feature_enabled == 2'b1,
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$sformatf("Feature enable is not 0b1 (%x)", feature_enabled));
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test.end_test();
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/// Upload part of feature 0, interrupt, then feature 1
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test.start_test("Checking feature 1 unlock after reset", 100us);
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ctrlport_poke32(FEATURE_ADDR, FEATURE0);
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ctrlport_poke32(KEY_ADDR, hash0_0);
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ctrlport_poke32(KEY_ADDR, hash0_1);
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ctrlport_poke32(KEY_ADDR, hash0_2);
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ctrlport_poke32(FEATURE_ADDR, FEATURE1);
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ctrlport_poke32(KEY_ADDR, hash1_0);
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ctrlport_poke32(KEY_ADDR, hash1_1);
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ctrlport_poke32(KEY_ADDR, hash1_2);
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ctrlport_poke32(KEY_ADDR, hash1_3);
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ctrlport_poke32(KEY_ADDR, hash1_4);
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ctrlport_poke32(KEY_ADDR, hash1_5);
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ctrlport_poke32(KEY_ADDR, hash1_6);
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ctrlport_poke32(KEY_ADDR, hash1_7);
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test.assert_error(feature_enabled == 2'b11,
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$sformatf("Feature enable is not 0b11 (%x)", feature_enabled));
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ctrlport_peek32(RB_ADDR, 32'b10000000000000000000000000000001);
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test.end_test();
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//--------------------------------
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// Finish Up
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//--------------------------------
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test.end_tb();
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end : tb_main
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endmodule : license_check_tb
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`default_nettype wire
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Reference in New Issue
Block a user