fpga: lib: Fix indentation in setting_reg.v

Original-commit: a7050773f206f55de99f36a742df628398e0aae1

lib/control/setting_reg.v

@@ -1,38 +1,43 @@
 //
 // Copyright 2011-2012 Ettus Research LLC
 // Copyright 2018 Ettus Research, a National Instruments Company
+// Copyright 2022 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
+// Module: setting_reg
+//
+// Description:
+//
+//   A settings register is a peripheral for the settings register bus. When
+//   the settings register sees the strobe and a matching address, the outputs
+//   will be become registered to the given input bus.
+//
 
-
+module setting_reg #(
-//----------------------------------------------------------------------
+  parameter my_addr  = 0,
-//-- A settings register is a peripheral for the settings register bus.
+  parameter awidth   = 8,
-//-- When the settings register sees strobe abd a matching address,
+  parameter width    = 32,
-//-- the outputs will be become registered to the given input bus.
+  parameter at_reset = 0
-//----------------------------------------------------------------------
+) (
-
+  input  wire              clk,
-module setting_reg
+  input  wire              rst,
-  #(parameter my_addr = 0, 
+  input  wire              strobe,
-    parameter awidth = 8,
+  input  wire [awidth-1:0] addr,
-    parameter width = 32,
+  input  wire [      31:0] in,
-    parameter at_reset=0)
+  output reg  [ width-1:0] out,
-    (input clk, input rst, input strobe, input wire [awidth-1:0] addr,
+  output reg               changed
-     input wire [31:0] in, output reg [width-1:0] out, output reg changed);
+);
-   
+  always @(posedge clk)
-   always @(posedge clk)
+    if(rst) begin
-     if(rst)
+      out <= at_reset;
-       begin
+      changed <= 1'b0;
-	  out <= at_reset;
+    end else begin
-	  changed <= 1'b0;
+      if(strobe && (my_addr == addr)) begin
-       end
+        out     <= in[width-1:0];
-     else
+        changed <= 1'b1;
-       if(strobe & (my_addr==addr))
+      end else begin
-	 begin
+        changed <= 1'b0;
-	    out <= in[width-1:0];
+      end
-	    changed <= 1'b1;
+    end
-	 end
-       else
-	 changed <= 1'b0;
-   
 endmodule // setting_reg