diff --git a/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
index 87c64d2..a7925ca 100644
--- a/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
+++ b/top/e320/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
@@ -32,7 +32,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -63,7 +63,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -94,7 +94,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -125,7 +125,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -156,7 +156,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -187,7 +187,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -218,7 +218,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -249,7 +249,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -280,7 +280,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -311,7 +311,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -342,7 +342,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -373,7 +373,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -404,7 +404,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -435,7 +435,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -466,7 +466,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -497,7 +497,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -517,337 +517,394 @@
100000000
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
false
100000000
0
@@ -859,7 +916,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -868,110 +925,131 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
@@ -983,90 +1061,108 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
@@ -1076,8 +1172,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
@@ -1088,7 +1185,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1101,24 +1198,29 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
0
100000000
+ 0
0
- 0.000
- 156.25
+ 0.0
+
+ 156250000
undef
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
0
@@ -1127,7 +1229,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -1140,7 +1242,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -1153,7 +1255,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1166,7 +1268,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1418,12 +1520,12 @@
TRUE
TRUE
IP_Flow
- 0
+ 6
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -1767,6 +1869,56 @@
+
+
+
diff --git a/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
index 26d7060..15add59 100644
--- a/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
+++ b/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -577,6 +582,22 @@
+
+
+
diff --git a/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
index 2f6ec0d..a84e91e 100644
--- a/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
+++ b/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -575,6 +580,22 @@
+
+
+
diff --git a/top/e320/ip/axi_eth_dma/axi_eth_dma.xci b/top/e320/ip/axi_eth_dma/axi_eth_dma.xci
index ec1df69..4a78139 100644
--- a/top/e320/ip/axi_eth_dma/axi_eth_dma.xci
+++ b/top/e320/ip/axi_eth_dma/axi_eth_dma.xci
@@ -35,7 +35,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -50,7 +50,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -63,7 +63,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -76,10 +76,10 @@
64
100000000
0
- 0
- 0
+ 1
+ 1
0
- 0
+ 1
0
0
1
@@ -90,7 +90,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_ONLY
0
@@ -99,8 +99,9 @@
0
100000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -109,10 +110,10 @@
64
100000000
1
- 0
- 0
+ 1
+ 1
0
- 0
+ 1
0
0
0
@@ -123,7 +124,7 @@
2
1
1
- 0.000
+ 0.0
AXI4
WRITE_ONLY
0
@@ -132,8 +133,9 @@
0
100000000
+ 0
0
- 0.000
+ 0.0
32
0
0
@@ -154,7 +156,7 @@
0
1
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -164,8 +166,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -177,7 +180,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -190,7 +193,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -218,7 +221,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -228,8 +231,9 @@
0
100000000
+ 0
0
- 0.000
+ 0.0
125
0
zynq
@@ -299,12 +303,12 @@
TRUE
TRUE
IP_Flow
- 20
+ 25
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -332,10 +336,7 @@
-
-
-
@@ -346,10 +347,7 @@
-
-
-
@@ -405,6 +403,73 @@
+
+
+
diff --git a/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl b/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl
index 779e780..0277744 100644
--- a/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl
+++ b/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
-set scripts_vivado_version 2019.1
+set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
- catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
- common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty."
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
- common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
- common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
- common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
-common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"."
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"."
if { $nRet != 0 } {
- catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
@@ -131,7 +131,7 @@ xilinx.com:ip:axi_protocol_converter:2.1\
"
set list_ips_missing ""
- common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
@@ -141,14 +141,14 @@ xilinx.com:ip:axi_protocol_converter:2.1\
}
if { $list_ips_missing ne "" } {
- catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
- common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
@@ -163,21 +163,21 @@ proc create_hier_cell_dma { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
- catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_dma() - Empty argument(s)!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dma() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
return
}
@@ -278,14 +278,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
return
}
@@ -498,30 +498,26 @@ proc create_root_design { parentCell } {
set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ]
set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ]
set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ]
- set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ]
+ set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_GP0_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \
- CONFIG.FREQ_HZ {40000000} \
] $S_AXI_GP0_ACLK
set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ]
- set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ]
+ set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk -freq_hz 40000000 S_AXI_HP0_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_HP0_ARESETN} \
- CONFIG.FREQ_HZ {40000000} \
] $S_AXI_HP0_ACLK
set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ]
- set bus_clk [ create_bd_port -dir I -type clk bus_clk ]
+ set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \
CONFIG.ASSOCIATED_RESET {bus_rstn} \
- CONFIG.FREQ_HZ {200000000} \
] $bus_clk
set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
- set clk40 [ create_bd_port -dir I -type clk clk40 ]
+ set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axi_net:m_axi_xbar:m_axi_eth_dma:m_axi_eth_internal} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
- CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
@@ -879,8 +875,12 @@ proc create_root_design { parentCell } {
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#UART 1#UART 1#PJTAG#PJTAG#PJTAG#PJTAG#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 0#UART 0#I2C 1#I2C 1#GPIO#GPIO#Enet 0#Enet 0} \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#tx#rx#tdi#tdo#tck#tms#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#scl#sda#gpio[50]#gpio[51]#mdc#mdio} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#UART 1#UART\
+1#PJTAG#PJTAG#PJTAG#PJTAG#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet\
+0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\
+0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 0#UART\
+0#I2C 1#I2C 1#GPIO#GPIO#Enet 0#Enet 0}\
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#tx#rx#tdi#tdo#tck#tms#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#scl#sda#gpio[50]#gpio[51]#mdc#mdio}\
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \
@@ -1057,21 +1057,21 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout]
# Create address segments
- create_bd_addr_seg -range 0x00004000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_dma_eth_internal/S_AXI_LITE/Reg] SEG_axi_dma_eth_internal_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_dma/Reg] SEG_m_axi_eth_dma_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40030000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_net/Reg] SEG_m_axi_net_Reg
- create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
- create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
- create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_HIGH_OCM] SEG_processing_system7_0_HP1_HIGH_OCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
- create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_HIGH_OCM] SEG_processing_system7_0_HP2_HIGH_OCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM
- create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
- create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM
- create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM
+ assign_bd_address -offset 0x40020000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_dma_eth_internal/S_AXI_LITE/Reg] -force
+ assign_bd_address -offset 0x40000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_dma/Reg] -force
+ assign_bd_address -offset 0x40030000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] -force
+ assign_bd_address -offset 0x40004000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_net/Reg] -force
+ assign_bd_address -offset 0x40010000 -range 0x00004000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] -force
+ assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_HIGH_OCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] -force
+ assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_HIGH_OCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] -force
+ assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] -force
# Restore current instance
diff --git a/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci
index 8888402..5c52fdf 100644
--- a/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci
+++ b/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -569,6 +574,14 @@
+
+
+
diff --git a/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci b/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci
index cc0f896..249357e 100644
--- a/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci
+++ b/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -571,6 +576,14 @@
+
+
+
diff --git a/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
index ae93c64..f108268 100644
--- a/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
+++ b/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
@@ -7,7 +7,7 @@
one_gig_eth_pcs_pma
-
+
1
1
@@ -16,51 +16,63 @@
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
false
false
false
@@ -69,37 +81,54 @@
+ 0
0
+ 0
0
false
100000000
+ 0
0
+ 0
0
100000000
+ 0
0
- 0.000
+ 0.0
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
100000000
0
- 0.000
+ 0.0
100000000
0
- 0.000
+ 0.0
false
false
false
@@ -110,14 +139,16 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
false
false
false
@@ -125,29 +156,35 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
ACTIVE_LOW
ACTIVE_LOW
@@ -176,7 +213,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -187,31 +224,38 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
true
0
+ 0
0
false
false
@@ -221,7 +265,7 @@
DIFF_PAIR_0
DIFF_PAIR_1
zynq
- 0
+ Sync
one_gig_eth_pcs_pma
50.0
false
@@ -314,12 +358,12 @@
TRUE
TRUE
IP_Flow
- 6
+ 4
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -345,6 +389,31 @@
+
+
+
diff --git a/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
index 140a504..f427db4 100644
--- a/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
+++ b/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
@@ -16,18 +16,21 @@
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -37,14 +40,16 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
false
0
@@ -53,83 +58,98 @@
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
false
0
0
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
ten_gig_eth_pcs_pma
78.125
@@ -179,12 +199,12 @@
TRUE
TRUE
IP_Flow
- 15
+ 19
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -193,6 +213,33 @@
+
+
+
diff --git a/top/e320/setupenv.sh b/top/e320/setupenv.sh
index 13f0b3b..5c3ea1c 100644
--- a/top/e320/setupenv.sh
+++ b/top/e320/setupenv.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-VIVADO_VER=2019.1
+VIVADO_VER=2021.1
DISPLAY_NAME="USRP-E320"
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)