From c38c6f1b3a52dd08ac749ec8f8b1f27ee1190811 Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Mon, 21 Feb 2022 11:17:25 +0100
Subject: [PATCH] Remove FSRU-related files

The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA
repository never had the relevant files, and the block controller also
never existed. This removes all the corresponding files from MPM, as
well as some references from makefiles.


Original-commit: ba00ff0cf5c0ced093e0be12b3006fe2f657a58a
---
 top/n3xx/setupenv.sh | 1 -
 1 file changed, 1 deletion(-)

diff --git a/top/n3xx/setupenv.sh b/top/n3xx/setupenv.sh
index bb20a33..d3057d5 100644
--- a/top/n3xx/setupenv.sh
+++ b/top/n3xx/setupenv.sh
@@ -8,7 +8,6 @@ declare -A PRODUCT_ID_MAP
 PRODUCT_ID_MAP["N300"]="zynq/xc7z035/ffg900/-2"
 PRODUCT_ID_MAP["N310"]="zynq/xc7z100/ffg900/-2"
 PRODUCT_ID_MAP["N320"]="zynq/xc7z100/ffg900/-2"
-PRODUCT_ID_MAP["EISCAT"]="zynq/xc7z100/ffg900/-2"
 
 # Set default part for simulation
 export ARCH=zynq