fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax

Original-commit: 4f2148e7cada5a66ce5eee92ca956cb22b31b98b

lib/rfnoc/utils/ctrlport_decoder.v

@@ -80,6 +80,7 @@ module ctrlport_decoder #(
 
   wire [NUM_SLAVES-1:0] decoder;
 
+  generate
     genvar i;
     for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
       // Check if the upper bits of the request address match each slave. If the
@@ -114,6 +115,7 @@ module ctrlport_decoder #(
         end
       end
     end
+  endgenerate
 
 
   //---------------------------------------------------------------------------