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fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax

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Original-commit: 4f2148e7cada5a66ce5eee92ca956cb22b31b98b
This commit is contained in:
Max Köhler
2020-07-10 15:12:55 -05:00
committed by Humberto Jimenez
parent 9ce170e4d5
commit c33435c1b9
1 changed files with 39 additions and 37 deletions
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lib/rfnoc/utils/ctrlport_decoder.v
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@@ -80,6 +80,7 @@ module ctrlport_decoder #(
wire [NUM_SLAVES-1:0] decoder; wire [NUM_SLAVES-1:0] decoder;
generate
genvar i; genvar i;
for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
// Check if the upper bits of the request address match each slave. If the // Check if the upper bits of the request address match each slave. If the
@@ -114,6 +115,7 @@ module ctrlport_decoder #(
end end
end end
end end
endgenerate
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------