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fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1

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Original-commit: dc738a7bdb200757d58b59de5c055e2cca467cf8
This commit is contained in:
Wade Fife
2020-05-12 13:46:28 -05:00
parent 8556184025
commit c2ca39a727
1 changed files with 64 additions and 48 deletions
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lib/rfnoc/utils/ctrlport_splitter.v
+20 -4
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@@ -60,11 +60,27 @@ module ctrlport_splitter #(
input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
);
generate
if (NUM_SLAVES == 1) begin : gen_no_split
// No logic is needed if only one slave is going to be connected
assign m_ctrlport_req_wr = s_ctrlport_req_wr;
assign m_ctrlport_req_rd = s_ctrlport_req_rd;
assign m_ctrlport_req_addr = s_ctrlport_req_addr;
assign m_ctrlport_req_data = s_ctrlport_req_data;
assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en;
assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
assign m_ctrlport_req_time = s_ctrlport_req_time;
always @(*) begin
s_ctrlport_resp_ack = m_ctrlport_resp_ack;
s_ctrlport_resp_status = m_ctrlport_resp_status;
s_ctrlport_resp_data = m_ctrlport_resp_data;
end
end else begin : gen_splitter
//---------------------------------------------------------------------------
// Split the requests among the slaves
//---------------------------------------------------------------------------
generate
genvar i;
for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
// No special logic is required to split the requests from the master among
@@ -77,7 +93,6 @@ module ctrlport_splitter #(
assign m_ctrlport_req_has_time[i] = s_ctrlport_req_has_time;
assign m_ctrlport_req_time[64*i+:64] = s_ctrlport_req_time;
end
endgenerate
//---------------------------------------------------------------------------
// Decode the responses
@@ -101,7 +116,7 @@ module ctrlport_splitter #(
end
// Register the output to break combinatorial path
always @(posedge ctrlport_clk) begin
always @(posedge ctrlport_clk) begin : response_reg
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 0;
end else begin
@@ -110,5 +125,6 @@ module ctrlport_splitter #(
s_ctrlport_resp_ack <= ack;
end
end
end
endgenerate
endmodule