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fpga: x400: Add DRAM support

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Original-commit: 19a333a2682898c4720a1316d4bcd6b3046d23ba
This commit is contained in:
Wade Fife
2022-02-07 13:08:11 -07:00
parent a265c582ff
commit c2477b9519
5 changed files with 1271 additions and 105 deletions
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top/x400/x4xx_core.v
+276 -47
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0
//
@@ -21,6 +21,7 @@
// MTU : Log2 of maximum transmission unit in CHDR_W sized words
// RFNOC_PROTOVER : RFNoC protocol version (major[7:0], minor[7:0])
// RADIO_SPC : Number of samples per radio clock cycle
// RF_BANDWIDTH : RF bandwidth of each radio channel
//
@@ -33,17 +34,54 @@ module x4xx_core #(
parameter CHDR_W = 64,
parameter MTU = $clog2(8192 / (CHDR_W/8)),
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter RADIO_SPC = 1
parameter RADIO_SPC = 1,
parameter RF_BANDWIDTH = 200
) (
// Clocks and resets
input radio_clk,
input radio_rst,
input radio_clk_2x,
input wire radio_clk,
input wire radio_rst,
input wire radio_clk_2x,
input rfnoc_chdr_clk,
input rfnoc_chdr_rst,
input rfnoc_ctrl_clk,
input rfnoc_ctrl_rst,
input wire rfnoc_chdr_clk,
input wire rfnoc_chdr_rst,
input wire rfnoc_ctrl_clk,
input wire rfnoc_ctrl_rst,
// DRAM Bank 0
input wire dram0_sys_clk_p,
input wire dram0_sys_clk_n,
output wire dram0_ck_t,
output wire dram0_ck_c,
output wire dram0_cs_n,
output wire dram0_act_n,
output wire [ 16:0] dram0_adr,
output wire [ 1:0] dram0_ba,
output wire dram0_bg,
output wire dram0_cke,
output wire dram0_odt,
output wire dram0_reset_n,
inout wire [ 7:0] dram0_dm_dbi_n,
inout wire [ 63:0] dram0_dq,
inout wire [ 7:0] dram0_dqs_t,
inout wire [ 7:0] dram0_dqs_c,
// DRAM Bank 1
input wire dram1_sys_clk_p,
input wire dram1_sys_clk_n,
output wire dram1_ck_t,
output wire dram1_ck_c,
output wire dram1_cs_n,
output wire dram1_act_n,
output wire [ 16:0] dram1_adr,
output wire [ 1:0] dram1_ba,
output wire dram1_bg,
output wire dram1_cke,
output wire dram1_odt,
output wire dram1_reset_n,
inout wire [ 7:0] dram1_dm_dbi_n,
inout wire [ 63:0] dram1_dq,
inout wire [ 7:0] dram1_dqs_t,
inout wire [ 7:0] dram1_dqs_c,
// AXI-Lite interface (for motherboard registers)
input s_axi_aclk,
@@ -185,44 +223,44 @@ module x4xx_core #(
`include "../../lib/rfnoc/core/ctrlport.vh"
axil_ctrlport_master
# (
.TIMEOUT (10), //integer:=10
.AXI_AWIDTH (REG_AWIDTH), //integer:=17
.CTRLPORT_AWIDTH (CTRLPORT_ADDR_W)) //integer:=17
axil_ctrlport_masterx (
.s_axi_aclk (s_axi_aclk), //in wire
.s_axi_aresetn (s_axi_aresetn), //in wire
.s_axi_awaddr (s_axi_awaddr), //in wire[(AXI_AWIDTH-1):0]
.s_axi_awvalid (s_axi_awvalid), //in wire
.s_axi_awready (s_axi_awready), //out wire
.s_axi_wdata (s_axi_wdata), //in wire[31:0]
.s_axi_wstrb (s_axi_wstrb), //in wire[3:0]
.s_axi_wvalid (s_axi_wvalid), //in wire
.s_axi_wready (s_axi_wready), //out wire
.s_axi_bresp (s_axi_bresp), //out wire[1:0]
.s_axi_bvalid (s_axi_bvalid), //out wire
.s_axi_bready (s_axi_bready), //in wire
.s_axi_araddr (s_axi_araddr), //in wire[(AXI_AWIDTH-1):0]
.s_axi_arvalid (s_axi_arvalid), //in wire
.s_axi_arready (s_axi_arready), //out wire
.s_axi_rdata (s_axi_rdata), //out wire[31:0]
.s_axi_rresp (s_axi_rresp), //out wire[1:0]
.s_axi_rvalid (s_axi_rvalid), //out wire
.s_axi_rready (s_axi_rready), //in wire
.m_ctrlport_req_wr (ctrlport_req_wr), //out wire
.m_ctrlport_req_rd (ctrlport_req_rd), //out wire
.m_ctrlport_req_addr (ctrlport_req_addr), //out wire[19:0]
.m_ctrlport_req_portid (ctrlport_req_portid), //out wire[9:0]
.m_ctrlport_req_rem_epid (ctrlport_req_rem_epid), //out wire[15:0]
.m_ctrlport_req_rem_portid (ctrlport_req_rem_portid), //out wire[9:0]
.m_ctrlport_req_data (ctrlport_req_data), //out wire[31:0]
.m_ctrlport_req_byte_en (ctrlport_req_byte_en), //out wire[3:0]
.m_ctrlport_req_has_time (ctrlport_req_has_time), //out wire
.m_ctrlport_req_time (ctrlport_req_time), //out wire[63:0]
.m_ctrlport_resp_ack (ctrlport_resp_ack), //in wire
.m_ctrlport_resp_status (ctrlport_resp_status), //in wire[1:0]
.m_ctrlport_resp_data (ctrlport_resp_data)); //in wire[31:0]
axil_ctrlport_master #(
.TIMEOUT (10 ),
.AXI_AWIDTH (REG_AWIDTH ),
.CTRLPORT_AWIDTH(CTRLPORT_ADDR_W)
) axil_ctrlport_master_i (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.m_ctrlport_req_wr (ctrlport_req_wr),
.m_ctrlport_req_rd (ctrlport_req_rd),
.m_ctrlport_req_addr (ctrlport_req_addr),
.m_ctrlport_req_portid (ctrlport_req_portid),
.m_ctrlport_req_rem_epid (ctrlport_req_rem_epid),
.m_ctrlport_req_rem_portid (ctrlport_req_rem_portid),
.m_ctrlport_req_data (ctrlport_req_data),
.m_ctrlport_req_byte_en (ctrlport_req_byte_en),
.m_ctrlport_req_has_time (ctrlport_req_has_time),
.m_ctrlport_req_time (ctrlport_req_time),
.m_ctrlport_resp_ack (ctrlport_resp_ack),
.m_ctrlport_resp_status (ctrlport_resp_status),
.m_ctrlport_resp_data (ctrlport_resp_data)
);
//---------------------------------------------------------------------------
@@ -352,6 +390,151 @@ module x4xx_core #(
assign radio_time_stb = rx_stb[0];
//---------------------------------------------------------------------------
// DRAM
//---------------------------------------------------------------------------
// Only the 100 and 200 MHz images currently support DRAM due to FPGA
// resource limitations. For 200 MHz and below, a 64-bit interface provides
// sufficient bandwidth.
localparam ENABLE_DRAM = (`ENABLE_DRAM) && (RF_BANDWIDTH <= 200);
localparam DRAM_NUM_PORTS = 4;
localparam DRAM_AXI_DWIDTH = (RF_BANDWIDTH <= 200) ? 64 : 128;
wire dram0_ui_clk;
wire dram0_ui_clk_sync_rst;
wire dram_clk = dram0_ui_clk;
wire dram_rst = dram0_ui_clk_sync_rst;
wire sys_rst = rfnoc_chdr_rst;
wire [ 32*DRAM_NUM_PORTS-1:0] dram_axi_araddr;
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_arburst;
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arcache;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arid;
wire [ 8*DRAM_NUM_PORTS-1:0] dram_axi_arlen;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arlock;
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_arprot;
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arqos;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arready;
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arregion;
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_arsize;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arvalid;
wire [ 32*DRAM_NUM_PORTS-1:0] dram_axi_awaddr;
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_awburst;
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awcache;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awid;
wire [ 8*DRAM_NUM_PORTS-1:0] dram_axi_awlen;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awlock;
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_awprot;
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awqos;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awready;
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awregion;
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_awsize;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awvalid;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bid;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bready;
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_bresp;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bvalid;
wire [ DRAM_AXI_DWIDTH*DRAM_NUM_PORTS-1:0] dram_axi_rdata;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rid;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rlast;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rready;
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_rresp;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rvalid;
wire [ DRAM_AXI_DWIDTH*DRAM_NUM_PORTS-1:0] dram_axi_wdata;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wlast;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wready;
wire [DRAM_AXI_DWIDTH/8*DRAM_NUM_PORTS-1:0] dram_axi_wstrb;
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wvalid;
x4xx_dram #(
.ENABLE_DRAM (ENABLE_DRAM),
.AXI_DWIDTH (DRAM_AXI_DWIDTH),
.NUM_PORTS (DRAM_NUM_PORTS)
) x4xx_dram_i (
.sys_rst (sys_rst),
.dram0_sys_clk_p (dram0_sys_clk_p),
.dram0_sys_clk_n (dram0_sys_clk_n),
.dram1_sys_clk_p (dram1_sys_clk_p),
.dram1_sys_clk_n (dram1_sys_clk_n),
.dram0_ui_clk (dram0_ui_clk),
.dram0_ui_clk_sync_rst (dram0_ui_clk_sync_rst),
.dram1_ui_clk (),
.dram1_ui_clk_sync_rst (),
.dram0_ck_t (dram0_ck_t),
.dram0_ck_c (dram0_ck_c),
.dram0_cs_n (dram0_cs_n),
.dram0_act_n (dram0_act_n),
.dram0_adr (dram0_adr),
.dram0_ba (dram0_ba),
.dram0_bg (dram0_bg),
.dram0_cke (dram0_cke),
.dram0_odt (dram0_odt),
.dram0_reset_n (dram0_reset_n),
.dram0_dm_dbi_n (dram0_dm_dbi_n),
.dram0_dq (dram0_dq),
.dram0_dqs_t (dram0_dqs_t),
.dram0_dqs_c (dram0_dqs_c),
.dram1_ck_t (dram1_ck_t),
.dram1_ck_c (dram1_ck_c),
.dram1_cs_n (dram1_cs_n),
.dram1_act_n (dram1_act_n),
.dram1_adr (dram1_adr),
.dram1_ba (dram1_ba),
.dram1_bg (dram1_bg),
.dram1_cke (dram1_cke),
.dram1_odt (dram1_odt),
.dram1_reset_n (dram1_reset_n),
.dram1_dm_dbi_n (dram1_dm_dbi_n),
.dram1_dq (dram1_dq),
.dram1_dqs_t (dram1_dqs_t),
.dram1_dqs_c (dram1_dqs_c),
.dram_clk (dram_clk),
.dram_rst (dram_rst),
.dram_init_calib_complete (),
.dram_axi_araddr (dram_axi_araddr),
.dram_axi_arburst (dram_axi_arburst),
.dram_axi_arcache (dram_axi_arcache),
.dram_axi_arid (dram_axi_arid),
.dram_axi_arlen (dram_axi_arlen),
.dram_axi_arlock (dram_axi_arlock),
.dram_axi_arprot (dram_axi_arprot),
.dram_axi_arqos (dram_axi_arqos),
.dram_axi_arready (dram_axi_arready),
.dram_axi_arregion (dram_axi_arregion),
.dram_axi_arsize (dram_axi_arsize),
.dram_axi_arvalid (dram_axi_arvalid),
.dram_axi_awaddr (dram_axi_awaddr),
.dram_axi_awburst (dram_axi_awburst),
.dram_axi_awcache (dram_axi_awcache),
.dram_axi_awid (dram_axi_awid),
.dram_axi_awlen (dram_axi_awlen),
.dram_axi_awlock (dram_axi_awlock),
.dram_axi_awprot (dram_axi_awprot),
.dram_axi_awqos (dram_axi_awqos),
.dram_axi_awready (dram_axi_awready),
.dram_axi_awregion (dram_axi_awregion),
.dram_axi_awsize (dram_axi_awsize),
.dram_axi_awvalid (dram_axi_awvalid),
.dram_axi_bid (dram_axi_bid),
.dram_axi_bready (dram_axi_bready),
.dram_axi_bresp (dram_axi_bresp),
.dram_axi_bvalid (dram_axi_bvalid),
.dram_axi_rdata (dram_axi_rdata),
.dram_axi_rid (dram_axi_rid),
.dram_axi_rlast (dram_axi_rlast),
.dram_axi_rready (dram_axi_rready),
.dram_axi_rresp (dram_axi_rresp),
.dram_axi_rvalid (dram_axi_rvalid),
.dram_axi_wdata (dram_axi_wdata),
.dram_axi_wlast (dram_axi_wlast),
.dram_axi_wready (dram_axi_wready),
.dram_axi_wstrb (dram_axi_wstrb),
.dram_axi_wvalid (dram_axi_wvalid)
);
//---------------------------------------------------------------------------
// RFNoC Image Core
//---------------------------------------------------------------------------
@@ -370,6 +553,7 @@ module x4xx_core #(
.core_arst (rfnoc_ctrl_rst),
.radio_clk (radio_clk),
.radio_2x_clk (radio_clk_2x),
.dram_clk (dram_clk),
.device_id (device_id),
.m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]),
.m_ctrlport_radio0_req_rd (ctrlport_radio_req_rd [0* 1+: 1]),
@@ -404,6 +588,51 @@ module x4xx_core #(
.radio_tx_data_radio0 ({ tx_data[1*CHAN_W+:CHAN_W], tx_data[0*CHAN_W+:CHAN_W]}),
.radio_tx_running_radio0 ({tx_running[1], tx_running[0] }),
.radio_time (radio_time),
.axi_rst (dram_rst),
.m_axi_awid (dram_axi_awid),
.m_axi_awaddr (dram_axi_awaddr),
.m_axi_awlen (dram_axi_awlen),
.m_axi_awsize (dram_axi_awsize),
.m_axi_awburst (dram_axi_awburst),
.m_axi_awlock (dram_axi_awlock),
.m_axi_awcache (dram_axi_awcache),
.m_axi_awprot (dram_axi_awprot),
.m_axi_awqos (dram_axi_awqos),
.m_axi_awregion (dram_axi_awregion),
.m_axi_awuser (),
.m_axi_awvalid (dram_axi_awvalid),
.m_axi_awready (dram_axi_awready),
.m_axi_wdata (dram_axi_wdata),
.m_axi_wstrb (dram_axi_wstrb),
.m_axi_wlast (dram_axi_wlast),
.m_axi_wuser (),
.m_axi_wvalid (dram_axi_wvalid),
.m_axi_wready (dram_axi_wready),
.m_axi_bid (dram_axi_bid),
.m_axi_bresp (dram_axi_bresp),
.m_axi_buser (0),
.m_axi_bvalid (dram_axi_bvalid),
.m_axi_bready (dram_axi_bready),
.m_axi_arid (dram_axi_arid),
.m_axi_araddr (dram_axi_araddr),
.m_axi_arlen (dram_axi_arlen),
.m_axi_arsize (dram_axi_arsize),
.m_axi_arburst (dram_axi_arburst),
.m_axi_arlock (dram_axi_arlock),
.m_axi_arcache (dram_axi_arcache),
.m_axi_arprot (dram_axi_arprot),
.m_axi_arqos (dram_axi_arqos),
.m_axi_arregion (dram_axi_arregion),
.m_axi_aruser (),
.m_axi_arvalid (dram_axi_arvalid),
.m_axi_arready (dram_axi_arready),
.m_axi_rid (dram_axi_rid),
.m_axi_rdata (dram_axi_rdata),
.m_axi_rresp (dram_axi_rresp),
.m_axi_rlast (dram_axi_rlast),
.m_axi_ruser (0),
.m_axi_rvalid (dram_axi_rvalid),
.m_axi_rready (dram_axi_rready),
.s_eth0_tdata (e2v_tdata [0*CHDR_W +: CHDR_W]),
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),