diff --git a/top/x400/regmap/x410/versioning_regs_regmap_utils.vh b/top/x400/regmap/x410/versioning_regs_regmap_utils.vh
index 08a123e..06b14d7 100644
--- a/top/x400/regmap/x410/versioning_regs_regmap_utils.vh
+++ b/top/x400/regmap/x410/versioning_regs_regmap_utils.vh
@@ -81,11 +81,11 @@
   localparam FPGA_VERSION_SIZE = 7;
   localparam FPGA_CURRENT_VERSION_BUILD            = 'h0;  // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
-  localparam FPGA_CURRENT_VERSION_MINOR            = 'h3;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
-  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h2;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
-  localparam FPGA_CURRENT_VERSION_MAJOR            = 'h8;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
-  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h8;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
-  localparam FPGA_VERSION_LAST_MODIFIED_TIME       = 'h23102410;  // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
+  localparam FPGA_CURRENT_VERSION_MINOR            = 'h0;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
+  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
+  localparam FPGA_CURRENT_VERSION_MAJOR            = 'h9;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
+  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h9;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
+  localparam FPGA_VERSION_LAST_MODIFIED_TIME       = 'h25020611;  // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
 
   // Enumerated type RF_CORE_100M_VERSION
   localparam RF_CORE_100M_VERSION_SIZE = 7;
diff --git a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh
index 0c05ea9..ef9a713 100644
--- a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh
+++ b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh
@@ -81,11 +81,11 @@
   localparam FPGA_VERSION_SIZE = 7;
   localparam FPGA_CURRENT_VERSION_BUILD            = 'h0;  // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
-  localparam FPGA_CURRENT_VERSION_MINOR            = 'h3;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
-  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h2;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
-  localparam FPGA_CURRENT_VERSION_MAJOR            = 'h8;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
-  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h8;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
-  localparam FPGA_VERSION_LAST_MODIFIED_TIME       = 'h23102410;  // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
+  localparam FPGA_CURRENT_VERSION_MINOR            = 'h0;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
+  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
+  localparam FPGA_CURRENT_VERSION_MAJOR            = 'h9;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
+  localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h9;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
+  localparam FPGA_VERSION_LAST_MODIFIED_TIME       = 'h25020611;  // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
 
   // Enumerated type RF_CORE_FULL_VERSION
   localparam RF_CORE_FULL_VERSION_SIZE = 7;
diff --git a/top/x400/x4xx.sv b/top/x400/x4xx.sv
index 80b6e42..c774eee 100644
--- a/top/x400/x4xx.sv
+++ b/top/x400/x4xx.sv
@@ -3111,13 +3111,13 @@ endmodule
 //        <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
 //        <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
 //      </info>
-//      <value name="FPGA_CURRENT_VERSION_MAJOR"           integer="8"/>
-//      <value name="FPGA_CURRENT_VERSION_MINOR"           integer="3"/>
+//      <value name="FPGA_CURRENT_VERSION_MAJOR"           integer="9"/>
+//      <value name="FPGA_CURRENT_VERSION_MINOR"           integer="0"/>
 //      <value name="FPGA_CURRENT_VERSION_BUILD"           integer="0"/>
-//      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="8"/>
-//      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="2"/>
+//      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="9"/>
+//      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
 //      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
-//      <value name="FPGA_VERSION_LAST_MODIFIED_TIME"      integer="0x23102410"/>
+//      <value name="FPGA_VERSION_LAST_MODIFIED_TIME"      integer="0x25020611"/>
 //    </enumeratedtype>
 //  </group>
 //</regmap>