fpga/mpm: x4xx: Add device DNA read capability

- Bumps FPGA compat from 8.2 to 8.3
- Adds three global motherboard registers to read the 96-bit device DNA
- MPM is updated to read these registers and update the device_info if
  compat version 8.3 is available


Original-commit: ad5f97f8284057b85ca98f47365c2a321edf7ece

top/x400/doc/X410/X410_FPGA_left.htm

@@ -367,7 +367,10 @@
         <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG');">QSFP_PORT_1_0_INFO_REG</span></p>        
         <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG');">QSFP_PORT_1_1_INFO_REG</span></p>        
         <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG');">QSFP_PORT_1_2_INFO_REG</span></p>        
-        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>      
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>        
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG');">DEVICE_DNA0_REG</span></p>        
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG');">DEVICE_DNA1_REG</span></p>        
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG');">DEVICE_DNA2_REG</span></p>      
       </div>    
     </div>    
     <p>

top/x400/doc/X410/X410_FPGA_right.htm

@@ -716,7 +716,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"
             <p>The top is defined in HDL source file x410_rfdc_regs.v, x4xx.v.</p>
             <div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
             <div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
-            <i><BR/><BR/>"All content provided is Copyright 2023 National Instruments Corporation.
+            <i><BR/><BR/>"All content provided is Copyright 2024 National Instruments Corporation.
 For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
             </i></div><BR/>
 </div>
@@ -8525,6 +8525,249 @@ Returns information from the QSFP1 Lane3.
 
 </div>
 
+</div>
+
+            <div class="register">
+              <a name="GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG"></a>
+            
+<h3 class="register">Offset 0x0100: DEVICE_DNA0_REG Register (R|W)</h3>
+
+                 <a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">show</span> extended info)</a>
+                 <div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">
+                 
+                <table class="extended_info">
+                
+<tr>
+
+<td class="outercell" rowspan="1">
+
+                  <table border="0" cellspacing="0" cellpadding="0">
+                    <tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
+                  </table>
+               
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right">DEVICE_DNA0_REG</td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0100</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0100
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
+
+</div>
+
+<div class="info">
+
+Least significant bytes of 12 byte device
+
+</div>
+
+</div>
+
+            <div class="register">
+              <a name="GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG"></a>
+            
+<h3 class="register">Offset 0x0104: DEVICE_DNA1_REG Register (R|W)</h3>
+
+                 <a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">show</span> extended info)</a>
+                 <div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">
+                 
+                <table class="extended_info">
+                
+<tr>
+
+<td class="outercell" rowspan="1">
+
+                  <table border="0" cellspacing="0" cellpadding="0">
+                    <tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
+                  </table>
+               
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right">DEVICE_DNA1_REG</td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0104</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0104
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
+
+</div>
+
+<div class="info">
+
+Second-least significant bytes of 12 byte device
+
+</div>
+
+</div>
+
+            <div class="register">
+              <a name="GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG"></a>
+            
+<h3 class="register">Offset 0x0108: DEVICE_DNA2_REG Register (R|W)</h3>
+
+                 <a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">show</span> extended info)</a>
+                 <div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">
+                 
+                <table class="extended_info">
+                
+<tr>
+
+<td class="outercell" rowspan="1">
+
+                  <table border="0" cellspacing="0" cellpadding="0">
+                    <tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
+                  </table>
+               
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right">DEVICE_DNA2_REG</td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0108</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0108
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
+
+</div>
+
+<div class="info">
+
+Most significant bytes of 12 byte device
+
+</div>
+
 </div>
 
 </div>
@@ -25139,7 +25382,7 @@ FPGA version.<BR/>
                             <td class='l'>0x00000002</td>
                             
                             <td class="l" style="text-align: left;">
-                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
+                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
                             
 </td>
 
@@ -25147,12 +25390,12 @@ FPGA version.<BR/>
 
 <tr valign="top">
 
-                        <td class='value'>2</td>
+                        <td class='value'>3</td>
                         
-                            <td class='l'>0x00000002</td>
+                            <td class='l'>0x00000003</td>
                             
                             <td class="l" style="text-align: left;">
-                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
+                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
                             
 </td>
 

top/x400/doc/X440/X440_FPGA_left.htm

@@ -394,7 +394,10 @@
         <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG');">QSFP_PORT_1_0_INFO_REG</span></p>        
         <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG');">QSFP_PORT_1_1_INFO_REG</span></p>        
         <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG');">QSFP_PORT_1_2_INFO_REG</span></p>        
-        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>      
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>        
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG');">DEVICE_DNA0_REG</span></p>        
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG');">DEVICE_DNA1_REG</span></p>        
+        <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG');">DEVICE_DNA2_REG</span></p>      
       </div>    
     </div>    
     <p>

top/x400/doc/X440/X440_FPGA_right.htm

@@ -715,7 +715,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"
             <p>The top is defined in HDL source file x440_rfdc_regs.v, x4xx.v.</p>
             <div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
             <div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
-            <i><BR/><BR/>"All content provided is Copyright 2023 National Instruments Corporation.
+            <i><BR/><BR/>"All content provided is Copyright 2024 National Instruments Corporation.
 For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
             </i></div><BR/>
 </div>
@@ -8811,6 +8811,249 @@ Returns information from the QSFP1 Lane3.
 
 </div>
 
+</div>
+
+            <div class="register">
+              <a name="GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG"></a>
+            
+<h3 class="register">Offset 0x0100: DEVICE_DNA0_REG Register (R|W)</h3>
+
+                 <a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">show</span> extended info)</a>
+                 <div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">
+                 
+                <table class="extended_info">
+                
+<tr>
+
+<td class="outercell" rowspan="1">
+
+                  <table border="0" cellspacing="0" cellpadding="0">
+                    <tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
+                  </table>
+               
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right">DEVICE_DNA0_REG</td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0100</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0100
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
+
+</div>
+
+<div class="info">
+
+Least significant bytes of 12 byte device
+
+</div>
+
+</div>
+
+            <div class="register">
+              <a name="GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG"></a>
+            
+<h3 class="register">Offset 0x0104: DEVICE_DNA1_REG Register (R|W)</h3>
+
+                 <a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">show</span> extended info)</a>
+                 <div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">
+                 
+                <table class="extended_info">
+                
+<tr>
+
+<td class="outercell" rowspan="1">
+
+                  <table border="0" cellspacing="0" cellpadding="0">
+                    <tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
+                  </table>
+               
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right">DEVICE_DNA1_REG</td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0104</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0104
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
+
+</div>
+
+<div class="info">
+
+Second-least significant bytes of 12 byte device
+
+</div>
+
+</div>
+
+            <div class="register">
+              <a name="GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG"></a>
+            
+<h3 class="register">Offset 0x0108: DEVICE_DNA2_REG Register (R|W)</h3>
+
+                 <a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">show</span> extended info)</a>
+                 <div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">
+                 
+                <table class="extended_info">
+                
+<tr>
+
+<td class="outercell" rowspan="1">
+
+                  <table border="0" cellspacing="0" cellpadding="0">
+                    <tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
+                  </table>
+               
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+  <tr><td class="offset_info" align="right">DEVICE_DNA2_REG</td></tr>
+  <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0108</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0108
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
+
+</div>
+
+<div class="info">
+
+Most significant bytes of 12 byte device
+
+</div>
+
 </div>
 
 </div>
@@ -29060,7 +29303,7 @@ FPGA version.<BR/>
                             <td class='l'>0x00000002</td>
                             
                             <td class="l" style="text-align: left;">
-                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
+                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
                             
 </td>
 
@@ -29068,12 +29311,12 @@ FPGA version.<BR/>
 
 <tr valign="top">
 
-                        <td class='value'>2</td>
+                        <td class='value'>3</td>
                         
-                            <td class='l'>0x00000002</td>
+                            <td class='l'>0x00000003</td>
                             
                             <td class="l" style="text-align: left;">
-                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
+                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
                             
 </td>
 

top/x400/regmap/global_regs_regmap_utils.vh

@@ -1,5 +1,5 @@
 //
-// Copyright 2023 Ettus Research, A National Instruments Company
+// Copyright 2024 Ettus Research, A National Instruments Company
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -40,6 +40,9 @@
   // QSFP_PORT_1_1_INFO_REG : 0x74 (x4xx_global_regs.v)
   // QSFP_PORT_1_2_INFO_REG : 0x78 (x4xx_global_regs.v)
   // QSFP_PORT_1_3_INFO_REG : 0x7C (x4xx_global_regs.v)
+  // DEVICE_DNA0_REG        : 0x100 (x4xx_global_regs.v)
+  // DEVICE_DNA1_REG        : 0x104 (x4xx_global_regs.v)
+  // DEVICE_DNA2_REG        : 0x108 (x4xx_global_regs.v)
 
 //===============================================================================
 // RegTypes
@@ -287,3 +290,18 @@
   localparam QSFP_PORT_1_3_INFO_REG = 'h7C; // Register Offset
   localparam QSFP_PORT_1_3_INFO_REG_SIZE = 32;  // register width in bits
   localparam QSFP_PORT_1_3_INFO_REG_MASK = 32'h0;
+
+  // DEVICE_DNA0_REG Register (from x4xx_global_regs.v)
+  localparam DEVICE_DNA0_REG = 'h100; // Register Offset
+  localparam DEVICE_DNA0_REG_SIZE = 32;  // register width in bits
+  localparam DEVICE_DNA0_REG_MASK = 32'h0;
+
+  // DEVICE_DNA1_REG Register (from x4xx_global_regs.v)
+  localparam DEVICE_DNA1_REG = 'h104; // Register Offset
+  localparam DEVICE_DNA1_REG_SIZE = 32;  // register width in bits
+  localparam DEVICE_DNA1_REG_MASK = 32'h0;
+
+  // DEVICE_DNA2_REG Register (from x4xx_global_regs.v)
+  localparam DEVICE_DNA2_REG = 'h108; // Register Offset
+  localparam DEVICE_DNA2_REG_SIZE = 32;  // register width in bits
+  localparam DEVICE_DNA2_REG_MASK = 32'h0;

top/x400/regmap/x410/versioning_regs_regmap_utils.vh

@@ -81,7 +81,7 @@
   localparam FPGA_VERSION_SIZE = 7;
   localparam FPGA_CURRENT_VERSION_BUILD            = 'h0;  // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
-  localparam FPGA_CURRENT_VERSION_MINOR            = 'h2;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
+  localparam FPGA_CURRENT_VERSION_MINOR            = 'h3;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h2;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
   localparam FPGA_CURRENT_VERSION_MAJOR            = 'h8;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h8;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR

top/x400/regmap/x440/versioning_regs_regmap_utils.vh

@@ -81,7 +81,7 @@
   localparam FPGA_VERSION_SIZE = 7;
   localparam FPGA_CURRENT_VERSION_BUILD            = 'h0;  // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
-  localparam FPGA_CURRENT_VERSION_MINOR            = 'h2;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
+  localparam FPGA_CURRENT_VERSION_MINOR            = 'h3;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h2;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
   localparam FPGA_CURRENT_VERSION_MAJOR            = 'h8;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h8;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR

top/x400/x4xx.v

@@ -3123,7 +3123,7 @@ endmodule
 //        <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
 //      </info>
 //      <value name="FPGA_CURRENT_VERSION_MAJOR"           integer="8"/>
-//      <value name="FPGA_CURRENT_VERSION_MINOR"           integer="2"/>
+//      <value name="FPGA_CURRENT_VERSION_MINOR"           integer="3"/>
 //      <value name="FPGA_CURRENT_VERSION_BUILD"           integer="0"/>
 //      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="8"/>
 //      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="2"/>

top/x400/x4xx_core.v

@@ -420,6 +420,8 @@ module x4xx_core #(
   wire [  2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status;
   wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data;
 
+  wire [95:0] device_dna;
+
   x4xx_core_common #(
     .CHDR_CLK_RATE   (CHDR_CLK_RATE),
     .CHDR_W          (CHDR_W),
@@ -517,7 +519,8 @@ module x4xx_core #(
     .mfg_test_en_fabric_clk           (mfg_test_en_fabric_clk),
     .mfg_test_en_gty_rcv_clk          (mfg_test_en_gty_rcv_clk),
     .fpga_aux_ref                     (fpga_aux_ref),
-    .version_info                     (version_info)
+    .version_info                     (version_info),
+    .device_dna                       (device_dna)
   );
 
   // Provide information for ctrlport timed commands
@@ -813,6 +816,7 @@ module x4xx_core #(
     .dram_clk                       (dram_clk),
     .ce_clk                         (ce_clk),
     .device_id                      (device_id),
+    .dna                            (device_dna),
     .m_ctrlport_radio0_req_wr       (ctrlport_radio_req_wr      [0* 1+: 1]),
     .m_ctrlport_radio0_req_rd       (ctrlport_radio_req_rd      [0* 1+: 1]),
     .m_ctrlport_radio0_req_addr     (ctrlport_radio_req_addr    [0*20+:20]),

top/x400/x4xx_core_common.v

@@ -159,8 +159,9 @@ module x4xx_core_common #(
 
   // Version (Constant)
   // Each component consists of a 96-bit vector (refer to versioning_utils.vh)
-  input wire [64*96-1:0] version_info
+  input wire [64*96-1:0] version_info,
 
+  input wire [95:0] device_dna
 );
 
   `include "regmap/radio_ctrlport_regmap_utils.vh"
@@ -304,7 +305,8 @@ module x4xx_core_common #(
     .mfg_test_en_fabric_clk  (mfg_test_en_fabric_clk),
     .mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk),
     .fpga_aux_ref            (fpga_aux_ref),
-    .device_id               (device_id)
+    .device_id               (device_id),
+    .device_dna              (device_dna)
   );
 
 

top/x400/x4xx_global_regs.v

@@ -73,7 +73,10 @@ module x4xx_global_regs #(
   input  wire        fpga_aux_ref,
 
   // Device ID used by RFNoC, transports, etc. (Domain: rfnoc_chdr_clk)
-  output reg [15:0] device_id
+  output reg [15:0] device_id,
+
+  // Device DNA (SoC serial)
+  input wire [95:0] device_dna
 );
 
   `include "../../lib/rfnoc/core/ctrlport.vh"
@@ -360,6 +363,16 @@ module x4xx_global_regs #(
             s_ctrlport_resp_data[MFG_TEST_FPGA_AUX_REF_FREQ_MSB:MFG_TEST_FPGA_AUX_REF_FREQ] <= fpga_aux_ref_freq;
           end
 
+          REG_BASE + DEVICE_DNA0_REG: begin
+            s_ctrlport_resp_data[31:0] <= device_dna[31:0];
+          end
+          REG_BASE + DEVICE_DNA1_REG: begin
+            s_ctrlport_resp_data[31:0] <= device_dna[63:32];
+          end
+          REG_BASE + DEVICE_DNA2_REG: begin
+            s_ctrlport_resp_data[31:0] <= device_dna[95:64];
+          end
+
           // No register implementation for provided address
           default: begin
             // Acknowledge and provide error status if address is in range
@@ -735,6 +748,15 @@ endmodule
 //        </info>
 //      </bitfield>
 //    </register>
+//    <register name="DEVICE_DNA0_REG" offset="0x100" size="32">
+//      <info>Least significant bytes of 12 byte device</info>
+//    </register>
+//    <register name="DEVICE_DNA1_REG" offset="0x104" size="32">
+//      <info>Second-least significant bytes of 12 byte device</info>
+//    </register>
+//    <register name="DEVICE_DNA2_REG" offset="0x108" size="32">
+//      <info>Most significant bytes of 12 byte device</info>
+//    </register>
 //  </group>
 //</regmap>
 //XmlParse xml_off