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fpga/mpm: x4xx: Add device DNA read capability

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- Bumps FPGA compat from 8.2 to 8.3
- Adds three global motherboard registers to read the 96-bit device DNA
- MPM is updated to read these registers and update the device_info if
  compat version 8.3 is available


Original-commit: ad5f97f8284057b85ca98f47365c2a321edf7ece
This commit is contained in:
Martin Braun
2024-06-11 10:20:07 +02:00
committed by Joerg Hofrichter
parent d006250dc1
commit ba5e431c5c
11 changed files with 558 additions and 20 deletions
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top/x400/regmap/global_regs_regmap_utils.vh
+19 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
// Copyright 2024 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -40,6 +40,9 @@
// QSFP_PORT_1_1_INFO_REG : 0x74 (x4xx_global_regs.v)
// QSFP_PORT_1_2_INFO_REG : 0x78 (x4xx_global_regs.v)
// QSFP_PORT_1_3_INFO_REG : 0x7C (x4xx_global_regs.v)
// DEVICE_DNA0_REG : 0x100 (x4xx_global_regs.v)
// DEVICE_DNA1_REG : 0x104 (x4xx_global_regs.v)
// DEVICE_DNA2_REG : 0x108 (x4xx_global_regs.v)
//===============================================================================
// RegTypes
@@ -287,3 +290,18 @@
localparam QSFP_PORT_1_3_INFO_REG = 'h7C; // Register Offset
localparam QSFP_PORT_1_3_INFO_REG_SIZE = 32; // register width in bits
localparam QSFP_PORT_1_3_INFO_REG_MASK = 32'h0;
// DEVICE_DNA0_REG Register (from x4xx_global_regs.v)
localparam DEVICE_DNA0_REG = 'h100; // Register Offset
localparam DEVICE_DNA0_REG_SIZE = 32; // register width in bits
localparam DEVICE_DNA0_REG_MASK = 32'h0;
// DEVICE_DNA1_REG Register (from x4xx_global_regs.v)
localparam DEVICE_DNA1_REG = 'h104; // Register Offset
localparam DEVICE_DNA1_REG_SIZE = 32; // register width in bits
localparam DEVICE_DNA1_REG_MASK = 32'h0;
// DEVICE_DNA2_REG Register (from x4xx_global_regs.v)
localparam DEVICE_DNA2_REG = 'h108; // Register Offset
localparam DEVICE_DNA2_REG_SIZE = 32; // register width in bits
localparam DEVICE_DNA2_REG_MASK = 32'h0;
top/x400/regmap/x410/versioning_regs_regmap_utils.vh
+1 -1
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@@ -81,7 +81,7 @@
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h2; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MINOR = 'h3; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h2; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
top/x400/regmap/x440/versioning_regs_regmap_utils.vh
+1 -1
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@@ -81,7 +81,7 @@
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h2; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MINOR = 'h3; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h2; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR