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fpga/mpm: x4xx: Add device DNA read capability

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- Bumps FPGA compat from 8.2 to 8.3
- Adds three global motherboard registers to read the 96-bit device DNA
- MPM is updated to read these registers and update the device_info if
  compat version 8.3 is available


Original-commit: ad5f97f8284057b85ca98f47365c2a321edf7ece
This commit is contained in:
Martin Braun
2024-06-11 10:20:07 +02:00
committed by Joerg Hofrichter
parent d006250dc1
commit ba5e431c5c
11 changed files with 558 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/doc/X410/X410_FPGA_left.htm
+4 -1
View File
@@ -367,7 +367,10 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG');">QSFP_PORT_1_0_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG');">QSFP_PORT_1_1_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG');">QSFP_PORT_1_2_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG');">DEVICE_DNA0_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG');">DEVICE_DNA1_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG');">DEVICE_DNA2_REG</span></p>
</div>
</div>
<p>
top/x400/doc/X410/X410_FPGA_right.htm
+248 -5
View File
@@ -716,7 +716,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"
<p>The top is defined in HDL source file x410_rfdc_regs.v, x4xx.v.</p>
<div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
<div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
<i><BR/><BR/>"All content provided is Copyright 2023 National Instruments Corporation.
<i><BR/><BR/>"All content provided is Copyright 2024 National Instruments Corporation.
For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
</i></div><BR/>
</div>
@@ -8525,6 +8525,249 @@ Returns information from the QSFP1 Lane3.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG"></a>
<h3 class="register">Offset 0x0100: DEVICE_DNA0_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_DNA0_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0100</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0100
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Least significant bytes of 12 byte device
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG"></a>
<h3 class="register">Offset 0x0104: DEVICE_DNA1_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_DNA1_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0104</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0104
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Second-least significant bytes of 12 byte device
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG"></a>
<h3 class="register">Offset 0x0108: DEVICE_DNA2_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_DNA2_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0108</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0108
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Most significant bytes of 12 byte device
</div>
</div>
</div>
@@ -25139,7 +25382,7 @@ FPGA version.<BR/>
<td class='l'>0x00000002</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
@@ -25147,12 +25390,12 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>2</td>
<td class='value'>3</td>
<td class='l'>0x00000002</td>
<td class='l'>0x00000003</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
top/x400/doc/X440/X440_FPGA_left.htm
+4 -1
View File
@@ -394,7 +394,10 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG');">QSFP_PORT_1_0_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG');">QSFP_PORT_1_1_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG');">QSFP_PORT_1_2_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG');">DEVICE_DNA0_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG');">DEVICE_DNA1_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG');">DEVICE_DNA2_REG</span></p>
</div>
</div>
<p>
top/x400/doc/X440/X440_FPGA_right.htm
+248 -5
View File
@@ -715,7 +715,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"
<p>The top is defined in HDL source file x440_rfdc_regs.v, x4xx.v.</p>
<div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
<div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
<i><BR/><BR/>"All content provided is Copyright 2023 National Instruments Corporation.
<i><BR/><BR/>"All content provided is Copyright 2024 National Instruments Corporation.
For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
</i></div><BR/>
</div>
@@ -8811,6 +8811,249 @@ Returns information from the QSFP1 Lane3.
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG"></a>
<h3 class="register">Offset 0x0100: DEVICE_DNA0_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA0_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_DNA0_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0100</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0100
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Least significant bytes of 12 byte device
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG"></a>
<h3 class="register">Offset 0x0104: DEVICE_DNA1_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA1_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_DNA1_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0104</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0104
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Second-least significant bytes of 12 byte device
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG"></a>
<h3 class="register">Offset 0x0108: DEVICE_DNA2_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|DEVICE_DNA2_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DEVICE_DNA2_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0108</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0108
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Most significant bytes of 12 byte device
</div>
</div>
</div>
@@ -29060,7 +29303,7 @@ FPGA version.<BR/>
<td class='l'>0x00000002</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
@@ -29068,12 +29311,12 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>2</td>
<td class='value'>3</td>
<td class='l'>0x00000002</td>
<td class='l'>0x00000003</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>