FPGA: Restore FIR filter in rx_frontend_gen3
The FIR filter applied gain. Removing it caused incorrect scaling and signals where every other sample was zero. Also parameterized heterodyne frontend processing so it would not use resources in images not requiring it. Signed-off-by: michael-west <michael.west@ettus.com> Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
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@@ -14,7 +14,10 @@ module fe_control #(
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parameter NUM_CHANNELS = 2,
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parameter [7:0] SR_FE_CHAN_OFFSET = 16,
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parameter [7:0] SR_TX_FE_BASE = 192,
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parameter [7:0] SR_RX_FE_BASE = 200
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parameter [7:0] SR_RX_FE_BASE = 200,
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parameter BYPASS_DC_OFFSET_CORR = 0,
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parameter BYPASS_IQ_COMP = 0,
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parameter BYPASS_HETERODYNE = 1
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)(
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input clk, input reset,
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// Commands from Radio Core
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@@ -37,7 +40,7 @@ module fe_control #(
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tx_frontend_gen3 #(
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.SR_OFFSET_I(SR_TX_OFFSET_I), .SR_OFFSET_Q(SR_TX_OFFSET_Q),.SR_MAG_CORRECTION(SR_TX_MAG_CORRECTION),
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.SR_PHASE_CORRECTION(SR_TX_PHASE_CORRECTION), .SR_MUX(SR_TX_MUX),
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.BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0),
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.BYPASS_DC_OFFSET_CORR(BYPASS_DC_OFFSET_CORR), .BYPASS_IQ_COMP(BYPASS_IQ_COMP),
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.DEVICE("7SERIES")
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) tx_fe_corr_i (
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.clk(clk), .reset(reset),
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@@ -56,7 +59,7 @@ module fe_control #(
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rx_frontend_gen3 #(
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.SR_MAG_CORRECTION(SR_RX_MAG_CORRECTION), .SR_PHASE_CORRECTION(SR_RX_PHASE_CORRECTION), .SR_OFFSET_I(SR_RX_OFFSET_I),
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.SR_OFFSET_Q(SR_RX_OFFSET_Q), .SR_IQ_MAPPING(SR_RX_IQ_MAPPING), .SR_HET_PHASE_INCR(SR_RX_HET_PHASE_INCR),
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.BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0), .BYPASS_REALMODE_DSP(0),
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.BYPASS_DC_OFFSET_CORR(BYPASS_DC_OFFSET_CORR), .BYPASS_IQ_COMP(BYPASS_IQ_COMP), .BYPASS_HETERODYNE(BYPASS_HETERODYNE),
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.DEVICE("7SERIES")
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) rx_fe_corr_i (
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.clk(clk), .reset(reset), .sync_in(time_sync),
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