n3xx: Swap out liberio for internal Ethernet

Original-commit: 3555ab052e231905df2a47ee107dfdfc9cd8e4e9

top/n3xx/dboards/mg/n3xx.v

@@ -336,7 +336,6 @@ module n3xx (
 
   // Internal connections to PS
   // HP0 -- High Performance port 0, FPGA is the master
-  wire [5:0]  S_AXI_HP0_AWID;
   wire [31:0] S_AXI_HP0_AWADDR;
   wire [2:0]  S_AXI_HP0_AWPROT;
   wire        S_AXI_HP0_AWVALID;
@@ -348,7 +347,6 @@ module n3xx (
   wire [1:0]  S_AXI_HP0_BRESP;
   wire        S_AXI_HP0_BVALID;
   wire        S_AXI_HP0_BREADY;
-  wire [5:0]  S_AXI_HP0_ARID;
   wire [31:0] S_AXI_HP0_ARADDR;
   wire [2:0]  S_AXI_HP0_ARPROT;
   wire        S_AXI_HP0_ARVALID;
@@ -369,7 +367,6 @@ module n3xx (
   wire [2:0]  S_AXI_HP0_ARSIZE;
 
   // GP0 -- General Purpose port 0, FPGA is the master
-  wire [4:0]  S_AXI_GP0_AWID;
   wire [31:0] S_AXI_GP0_AWADDR;
   wire [2:0]  S_AXI_GP0_AWPROT;
   wire        S_AXI_GP0_AWVALID;
@@ -381,7 +378,6 @@ module n3xx (
   wire [1:0]  S_AXI_GP0_BRESP;
   wire        S_AXI_GP0_BVALID;
   wire        S_AXI_GP0_BREADY;
-  wire [4:0]  S_AXI_GP0_ARID;
   wire [31:0] S_AXI_GP0_ARADDR;
   wire [2:0]  S_AXI_GP0_ARPROT;
   wire        S_AXI_GP0_ARVALID;
@@ -490,6 +486,7 @@ module n3xx (
   wire [1:0]  M_AXI_GP0_RRESP;
   wire [31:0] M_AXI_GP0_RDATA;
 
+  // ETH DMA
   wire        M_AXI_ETH_DMA0_ARVALID;
   wire        M_AXI_ETH_DMA0_AWVALID;
   wire        M_AXI_ETH_DMA0_BREADY;
@@ -511,6 +508,23 @@ module n3xx (
   wire [1:0]  M_AXI_ETH_DMA0_BRESP;
   wire [1:0]  M_AXI_ETH_DMA0_RRESP;
   wire [31:0] M_AXI_ETH_DMA0_RDATA;
+  wire        m_axi_eth_internal_arvalid;
+  wire        m_axi_eth_internal_awvalid;
+  wire        m_axi_eth_internal_bready;
+  wire        m_axi_eth_internal_rready;
+  wire        m_axi_eth_internal_wvalid;
+  wire [31:0] m_axi_eth_internal_araddr;
+  wire [31:0] m_axi_eth_internal_awaddr;
+  wire [31:0] m_axi_eth_internal_wdata;
+  wire [3:0]  m_axi_eth_internal_wstrb;
+  wire        m_axi_eth_internal_arready;
+  wire        m_axi_eth_internal_awready;
+  wire        m_axi_eth_internal_bvalid;
+  wire        m_axi_eth_internal_rvalid;
+  wire        m_axi_eth_internal_wready;
+  wire [1:0]  m_axi_eth_internal_bresp;
+  wire [1:0]  m_axi_eth_internal_rresp;
+  wire [31:0] m_axi_eth_internal_rdata;
 
   wire        M_AXI_NET0_ARVALID;
   wire        M_AXI_NET0_AWVALID;
@@ -1613,15 +1627,25 @@ module n3xx (
   wire          e10_tlast, e10_tvalid, e10_tready;
 
 
-  // DMA xport adapter to PS
+// Internal Ethernet xport adapter to PS
+  wire [63:0] h2e_tdata;
+  wire [7:0]  h2e_tkeep;
+  wire        h2e_tlast;
+  wire        h2e_tready;
+  wire        h2e_tvalid;
+
+  wire [63:0] e2h_tdata;
+  wire [7:0]  e2h_tkeep;
+  wire        e2h_tlast;
+  wire        e2h_tready;
+  wire        e2h_tvalid;
+
   wire [63:0] m_axis_dma_tdata;
-  wire [3:0]  m_axis_dma_tuser;
   wire        m_axis_dma_tlast;
   wire        m_axis_dma_tready;
   wire        m_axis_dma_tvalid;
 
   wire [63:0] s_axis_dma_tdata;
-  wire [3:0]  s_axis_dma_tdest;
   wire        s_axis_dma_tlast;
   wire        s_axis_dma_tready;
   wire        s_axis_dma_tvalid;
@@ -1933,8 +1957,6 @@ module n3xx (
   assign  IRQ_F2P[0] = arm_eth0_rx_irq;
   assign  IRQ_F2P[1] = arm_eth0_tx_irq;
 
-  assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0;
-  assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0;
 
 `ifdef QSFP_10GBE
   // QSFP+ lanes connect to DMA engines and crossbar
@@ -2533,6 +2555,81 @@ module n3xx (
   );
 `endif
 
+  /////////////////////////////////////////////////////////////////////
+  //
+  // Internal Ethernet Interface
+  //
+  //////////////////////////////////////////////////////////////////////
+  eth_internal #(
+    .DWIDTH(REG_DWIDTH),
+    .AWIDTH(REG_AWIDTH),
+    .PORTNUM(8'd1)
+  ) eth_internal_i (
+    // Resets
+    .bus_rst (bus_rst),
+    // Clocks
+    .bus_clk (bus_clk),
+
+    //Axi-lite
+    .s_axi_aclk     (clk40),
+    .s_axi_aresetn  (clk40_rstn),
+    .s_axi_awaddr   (m_axi_eth_internal_awaddr),
+    .s_axi_awvalid  (m_axi_eth_internal_awvalid),
+    .s_axi_awready  (m_axi_eth_internal_awready),
+
+    .s_axi_wdata    (m_axi_eth_internal_wdata),
+    .s_axi_wstrb    (m_axi_eth_internal_wstrb),
+    .s_axi_wvalid   (m_axi_eth_internal_wvalid),
+    .s_axi_wready   (m_axi_eth_internal_wready),
+
+    .s_axi_bresp    (m_axi_eth_internal_bresp),
+    .s_axi_bvalid   (m_axi_eth_internal_bvalid),
+    .s_axi_bready   (m_axi_eth_internal_bready),
+
+    .s_axi_araddr   (m_axi_eth_internal_araddr),
+    .s_axi_arvalid  (m_axi_eth_internal_arvalid),
+    .s_axi_arready  (m_axi_eth_internal_arready),
+
+    .s_axi_rdata    (m_axi_eth_internal_rdata),
+    .s_axi_rresp    (m_axi_eth_internal_rresp),
+    .s_axi_rvalid   (m_axi_eth_internal_rvalid),
+    .s_axi_rready   (m_axi_eth_internal_rready),
+
+    // Host-Ethernet DMA interface
+    .e2h_tdata    (e2h_tdata),
+    .e2h_tkeep    (e2h_tkeep),
+    .e2h_tlast    (e2h_tlast),
+    .e2h_tvalid   (e2h_tvalid),
+    .e2h_tready   (e2h_tready),
+
+    .h2e_tdata    (h2e_tdata),
+    .h2e_tkeep    (h2e_tkeep),
+    .h2e_tlast    (h2e_tlast),
+    .h2e_tvalid   (h2e_tvalid),
+    .h2e_tready   (h2e_tready),
+
+    // Vita router interface
+    .e2v_tdata    (m_axis_dma_tdata),
+    .e2v_tlast    (m_axis_dma_tlast),
+    .e2v_tvalid   (m_axis_dma_tvalid),
+    .e2v_tready   (m_axis_dma_tready),
+
+    .v2e_tdata    (s_axis_dma_tdata),
+    .v2e_tlast    (s_axis_dma_tlast),
+    .v2e_tvalid   (s_axis_dma_tvalid),
+    .v2e_tready   (s_axis_dma_tready),
+
+    // MISC
+    .port_info    (),
+    .device_id    (device_id),
+
+    .link_up      (),
+    .activity     ()
+
+  );
+
+
+
   /////////////////////////////////////////////////////////////////////
   //
   // Processing System
@@ -2661,6 +2758,26 @@ module n3xx (
     .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB),
     .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID),
 
+    .m_axi_eth_internal_araddr(m_axi_eth_internal_araddr),
+    .m_axi_eth_internal_arprot(),
+    .m_axi_eth_internal_arready(m_axi_eth_internal_arready),
+    .m_axi_eth_internal_arvalid(m_axi_eth_internal_arvalid),
+    .m_axi_eth_internal_awaddr(m_axi_eth_internal_awaddr),
+    .m_axi_eth_internal_awprot(),
+    .m_axi_eth_internal_awready(m_axi_eth_internal_awready),
+    .m_axi_eth_internal_awvalid(m_axi_eth_internal_awvalid),
+    .m_axi_eth_internal_bready(m_axi_eth_internal_bready),
+    .m_axi_eth_internal_bresp(m_axi_eth_internal_bresp),
+    .m_axi_eth_internal_bvalid(m_axi_eth_internal_bvalid),
+    .m_axi_eth_internal_rdata(m_axi_eth_internal_rdata),
+    .m_axi_eth_internal_rready(m_axi_eth_internal_rready),
+    .m_axi_eth_internal_rresp(m_axi_eth_internal_rresp),
+    .m_axi_eth_internal_rvalid(m_axi_eth_internal_rvalid),
+    .m_axi_eth_internal_wdata(m_axi_eth_internal_wdata),
+    .m_axi_eth_internal_wready(m_axi_eth_internal_wready),
+    .m_axi_eth_internal_wstrb(m_axi_eth_internal_wstrb),
+    .m_axi_eth_internal_wvalid(m_axi_eth_internal_wvalid),
+
     .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR),
     .M_AXI_JESD0_arprot(),
     .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY),
@@ -2830,7 +2947,6 @@ module n3xx (
     .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR),
     .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST),
     .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE),
-    .S_AXI_GP0_arid(S_AXI_GP0_ARID),
     .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN),
     .S_AXI_GP0_arlock(1'b0),
     .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT),
@@ -2841,7 +2957,6 @@ module n3xx (
     .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR),
     .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST),
     .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE),
-    .S_AXI_GP0_awid(S_AXI_GP0_AWID),
     .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN),
     .S_AXI_GP0_awlock(1'b0),
     .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT),
@@ -2850,12 +2965,10 @@ module n3xx (
     .S_AXI_GP0_awready(S_AXI_GP0_AWREADY),
     .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE),
     .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID),
-    .S_AXI_GP0_bid(),
     .S_AXI_GP0_bready(S_AXI_GP0_BREADY),
     .S_AXI_GP0_bresp(S_AXI_GP0_BRESP),
     .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID),
     .S_AXI_GP0_rdata(S_AXI_GP0_RDATA),
-    .S_AXI_GP0_rid(),
     .S_AXI_GP0_rlast(S_AXI_GP0_RLAST),
     .S_AXI_GP0_rready(S_AXI_GP0_RREADY),
     .S_AXI_GP0_rresp(S_AXI_GP0_RRESP),
@@ -2912,31 +3025,29 @@ module n3xx (
     .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR),
     .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST),
     .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE),
-    .S_AXI_HP0_arid(S_AXI_HP0_ARID),
     .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN),
     .S_AXI_HP0_arlock(1'b0),
     .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT),
     .S_AXI_HP0_arqos(4'b0000),
     .S_AXI_HP0_arready(S_AXI_HP0_ARREADY),
+    .S_AXI_HP0_arregion(4'b0),
     .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE),
     .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID),
     .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR),
     .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST),
     .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE),
-    .S_AXI_HP0_awid(S_AXI_HP0_AWID),
     .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN),
     .S_AXI_HP0_awlock(1'b0),
     .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT),
     .S_AXI_HP0_awqos(4'b0000),
     .S_AXI_HP0_awready(S_AXI_HP0_AWREADY),
+    .S_AXI_HP0_awregion(4'b0),
     .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE),
     .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID),
-    .S_AXI_HP0_bid(),
     .S_AXI_HP0_bready(S_AXI_HP0_BREADY),
     .S_AXI_HP0_bresp(S_AXI_HP0_BRESP),
     .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID),
     .S_AXI_HP0_rdata(S_AXI_HP0_RDATA),
-    .S_AXI_HP0_rid(),
     .S_AXI_HP0_rlast(S_AXI_HP0_RLAST),
     .S_AXI_HP0_rready(S_AXI_HP0_RREADY),
     .S_AXI_HP0_rresp(S_AXI_HP0_RRESP),
@@ -2988,16 +3099,16 @@ module n3xx (
     .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID),
 
     // ARM DMA
-    .s_axis_dma_tdata(s_axis_dma_tdata),
+    .s_axis_dma_tdata(e2h_tdata),
-    .s_axis_dma_tdest(s_axis_dma_tdest),
+    .s_axis_dma_tkeep(e2h_tkeep),
-    .s_axis_dma_tlast(s_axis_dma_tlast),
+    .s_axis_dma_tlast(e2h_tlast),
-    .s_axis_dma_tready(s_axis_dma_tready),
+    .s_axis_dma_tready(e2h_tready),
-    .s_axis_dma_tvalid(s_axis_dma_tvalid),
+    .s_axis_dma_tvalid(e2h_tvalid),
-    .m_axis_dma_tdata(m_axis_dma_tdata),
+    .m_axis_dma_tdata(h2e_tdata),
-    .m_axis_dma_tuser(m_axis_dma_tuser),
+    .m_axis_dma_tkeep(h2e_tkeep),
-    .m_axis_dma_tlast(m_axis_dma_tlast),
+    .m_axis_dma_tlast(h2e_tlast),
-    .m_axis_dma_tready(m_axis_dma_tready),
+    .m_axis_dma_tready(h2e_tready),
-    .m_axis_dma_tvalid(m_axis_dma_tvalid),
+    .m_axis_dma_tvalid(h2e_tvalid),
 
     // Misc Interrupts, GPIO, clk
     .IRQ_F2P(IRQ_F2P),
@@ -3545,15 +3656,13 @@ module n3xx (
     .ddr3_axi_rvalid           (ddr3_axi_rvalid),
     .ddr3_axi_rready           (ddr3_axi_rready),
 
-    // DMA to PS
+    // Internal Ethernet DMA to PS
     .m_dma_tdata(s_axis_dma_tdata),
-    .m_dma_tdest(s_axis_dma_tdest),
     .m_dma_tlast(s_axis_dma_tlast),
     .m_dma_tready(s_axis_dma_tready),
     .m_dma_tvalid(s_axis_dma_tvalid),
 
     .s_dma_tdata(m_axis_dma_tdata),
-    .s_dma_tuser(m_axis_dma_tuser),
     .s_dma_tlast(m_axis_dma_tlast),
     .s_dma_tready(m_axis_dma_tready),
     .s_dma_tvalid(m_axis_dma_tvalid),

top/n3xx/dts/dma-common.dtsi

@@ -1,588 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
- * Copyright (c) 2017 National Instruments Corp
+ * Copyright (c) 2018 National Instruments Corp
- *
- * SPDX-License-Identifier: GPL-2.0 OR X11
  */
 
 &fpga_full {
-	tx_dma0: dma@43CA0000 {
+	nixge_internal: ethernet@40040000 {
-		compatible = "adi,axi-dmac-1.00.a";
+		#address-cells = <1>;
-		reg = <0x43CA0000 0x10000>;
+		#size-cells = <1>;
-		interrupts = <0 53 4>;
+		compatible = "ni,xge-enet-3.00";
-		interrupt-parent = <&intc>;
+		reg = <0x40040000 0x4000
-		clocks = <&clkc 15>;
+		       0x40050000 0x2000>;
-		#dma-cells = <1>;
+		reg-names = "dma", "ctrl";
-		adi,channels {
+			clocks = <&clkc 15>;
-			#size-cells = <0>;
+			clock-names = "bus_clk";
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma1: dma@43CB0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CB0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma2: dma@43CC0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CC0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma3: dma@43CD0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CD0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma4: dma@43CE0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CE0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma5: dma@43CF0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CF0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma6: dma@43D00000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43D00000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma7: dma@43D10000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43D10000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma8: dma@43D20000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43D20000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma9: dma@43D30000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43D30000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma0: dma@43C00000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C00000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma1: dma@43C10000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C10000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma2: dma@43C20000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C20000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma3: dma@43C30000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C30000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma4: dma@43C40000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C40000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma5: dma@43C50000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C50000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma6: dma@43C60000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C60000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma7: dma@43C70000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C70000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma8: dma@43C80000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C80000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma9: dma@43C90000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C90000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
 
-
+		interrupts = <0 52 4>, <0 53 4>;
-	usrp_rx_dma0: usrp-rx-dma@43c00000 {
+		interrupt-names = "rx", "tx";
-		compatible = "ettus,usrp-rx-dma";
+		interrupt-parent = <&intc>;
-		dmas = <&rx_dma0 0>;
-		dma-names = "dma";
-		port-id = <0>;
 		status = "okay";
 
-		regmap = <&dma_conf0>;
+		phy-mode = "internal";
-		offset = <0x0>;
+		local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
+
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
 	};
 
-	usrp_rx_dma1: usrp-rx-dma@43c10000 {
+	uio@40052000 {
-		compatible = "ettus,usrp-rx-dma";
+		compatible = "usrp-uio";
-		dmas = <&rx_dma1 0>;
+		reg = <0x40052000 0x2000>;
-		dma-names = "dma";
+		reg-names = "misc-enet-int-regs";
-		port-id = <1>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x4>;
-	};
-
-	usrp_rx_dma2: usrp-rx-dma@43c20000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma2 0>;
-		dma-names = "dma";
-		port-id = <2>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x8>;
-	};
-
-	usrp_rx_dma3: usrp-rx-dma@43c30000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma3 0>;
-		dma-names = "dma";
-		port-id = <3>;
-
-		regmap = <&dma_conf0>;
-		offset = <0xc>;
-	};
-
-	usrp_rx_dma4: usrp-rx-dma@43c40000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma4 0>;
-		dma-names = "dma";
-		port-id = <4>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x10>;
-	};
-
-	usrp_rx_dma5: usrp-rx-dma@43c50000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma5 0>;
-		dma-names = "dma";
-		port-id = <5>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x14>;
-	};
-
-	usrp_rx_dma6: usrp-rx-dma@43c60000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma6 0>;
-		dma-names = "dma";
-		port-id = <6>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x18>;
-	};
-
-	usrp_rx_dma7: usrp-rx-dma@43c70000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma7 0>;
-		dma-names = "dma";
-		port-id = <7>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x1c>;
-	};
-
-	usrp_rx_dma8: usrp-rx-dma@43c80000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma8 0>;
-		dma-names = "dma";
-		port-id = <8>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x20>;
-	};
-
-	usrp_rx_dma9: usrp-rx-dma@43c90000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma9 0>;
-		dma-names = "dma";
-		port-id = <9>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x24>;
-	};
-
-	usrp_tx_dma0: usrp-tx-dma@43ca0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma0 0>;
-		dma-names = "dma";
-		port-id = <0>;
-	};
-
-	usrp_tx_dma1: usrp-tx-dma@43cb0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma1 0>;
-		dma-names = "dma";
-		port-id = <1>;
-	};
-
-	usrp_tx_dma2: usrp-tx-dma@43cc0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma2 0>;
-		dma-names = "dma";
-		port-id = <2>;
-		status = "okay";
-	};
-
-	usrp_tx_dma3: usrp-tx-dma@43cd0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma3 0>;
-		dma-names = "dma";
-		port-id = <3>;
-	};
-
-	usrp_tx_dma4: usrp-tx-dma@43ce0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma4 0>;
-		dma-names = "dma";
-		port-id = <4>;
-		status = "okay";
-	};
-
-	usrp_tx_dma5: usrp-tx-dma@43cf0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma5 0>;
-		dma-names = "dma";
-		port-id = <5>;
-	};
-
-	usrp_tx_dma6: usrp-tx-dma@43d00000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma6 0>;
-		dma-names = "dma";
-		port-id = <6>;
-	};
-
-	usrp_tx_dma7: usrp-tx-dma@43d10000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma7 0>;
-		dma-names = "dma";
-		port-id = <7>;
-	};
-
-	usrp_tx_dma8: usrp-tx-dma@43d20000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma8 0>;
-		dma-names = "dma";
-		port-id = <8>;
-	};
-
-	usrp_tx_dma9: usrp-tx-dma@43d30000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma9 0>;
-		dma-names = "dma";
-		port-id = <9>;
-	};
-
-	dma_conf0: dma_conf0@42080000 {
-		compatible = "syscon";
-		reg = <0x42080000 0x1000>;
 		status = "okay";
 	};
 };

top/n3xx/n3xx_core.v

@@ -105,13 +105,11 @@ module n3xx_core #(
 
   // DMA xport adapter to PS
   input wire  [63:0] s_dma_tdata,
-  input wire  [3:0]  s_dma_tuser,
   input wire         s_dma_tlast,
   output wire        s_dma_tready,
   input wire         s_dma_tvalid,
 
   output wire [63:0] m_dma_tdata,
-  output wire [3:0]  m_dma_tdest,
   output wire        m_dma_tlast,
   input wire         m_dma_tready,
   output wire        m_dma_tvalid,
@@ -489,49 +487,6 @@ module n3xx_core #(
     end
   end
 
-  /////////////////////////////////////////////////////////////////////////////
-  //
-  // DMA Transport Adapter
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  wire [63:0] dmao_tdata;
-  wire        dmao_tlast;
-  wire        dmao_tvalid;
-  wire        dmao_tready;
-
-  wire [63:0] dmai_tdata;
-  wire        dmai_tlast;
-  wire        dmai_tvalid;
-  wire        dmai_tready;
-
-  liberio_chdr64_adapter #(
-    .DMA_ID_WIDTH                    (4)
-  ) dma_xport_adapter (
-    .clk                             (bus_clk),
-    .rst                             (bus_rst),
-    .device_id                       (device_id),
-    // From DMA engine to core
-    .s_dma_tdata                     (s_dma_tdata),
-    .s_dma_tuser                     (s_dma_tuser),
-    .s_dma_tlast                     (s_dma_tlast),
-    .s_dma_tvalid                    (s_dma_tvalid),
-    .s_dma_tready                    (s_dma_tready),
-    // From core to DMA engine
-    .m_dma_tdata                     (m_dma_tdata),
-    .m_dma_tuser                     (m_dma_tdest),
-    .m_dma_tlast                     (m_dma_tlast),
-    .m_dma_tvalid                    (m_dma_tvalid),
-    .m_dma_tready                    (m_dma_tready),
-    // CHDR buses
-    .s_chdr_tdata                    (dmao_tdata),
-    .s_chdr_tlast                    (dmao_tlast),
-    .s_chdr_tvalid                   (dmao_tvalid),
-    .s_chdr_tready                   (dmao_tready),
-    .m_chdr_tdata                    (dmai_tdata),
-    .m_chdr_tlast                    (dmai_tlast),
-    .m_chdr_tvalid                   (dmai_tvalid),
-    .m_chdr_tready                   (dmai_tready)
-  );
 
   /////////////////////////////////////////////////////////////////////
   //
@@ -1033,6 +988,12 @@ module n3xx_core #(
   );
 
 
+  /////////////////////////////////////////////////////////////////////////////
+  //
+  // RFNoC Image Core
+  //
+  /////////////////////////////////////////////////////////////////////////////
+
   // Unused memory AXI ports
   for (i = 0; i < NUM_DRAM_FIFOS; i = i+1) begin : gen_unused_ram_signals
     assign dram_axi_buser[i] = 4'b0;
@@ -1163,14 +1124,14 @@ module n3xx_core #(
     .m_eth1_tlast            (v2e1_tlast ),
     .m_eth1_tvalid           (v2e1_tvalid),
     .m_eth1_tready           (v2e1_tready),
-    .s_dma_tdata             (dmai_tdata),
+    .s_dma_tdata             (s_dma_tdata),
-    .s_dma_tlast             (dmai_tlast),
+    .s_dma_tlast             (s_dma_tlast),
-    .s_dma_tvalid            (dmai_tvalid),
+    .s_dma_tvalid            (s_dma_tvalid),
-    .s_dma_tready            (dmai_tready),
+    .s_dma_tready            (s_dma_tready),
-    .m_dma_tdata             (dmao_tdata),
+    .m_dma_tdata             (m_dma_tdata),
-    .m_dma_tlast             (dmao_tlast),
+    .m_dma_tlast             (m_dma_tlast),
-    .m_dma_tvalid            (dmao_tvalid),
+    .m_dma_tvalid            (m_dma_tvalid),
-    .m_dma_tready            (dmao_tready)
+    .m_dma_tready            (m_dma_tready)
   );