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fpga: Update all RFNoC image core files

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Original-commit: 0fca5d5ffda1f5f4f7c966c3e5f5200222a5a575
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent fae19151c4
commit aeaf219f77
26 changed files with 2604 additions and 2161 deletions
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top/e31x/e310_rfnoc_image_core.v
+73 -58
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,16 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:33.806116
// Source: e310_rfnoc_image_core.yml // Source: e310_rfnoc_image_core.yml
// Source SHA256: 8e0bdf84e7b65cbc1ad575d1d0a2fdcc33632fe69e8ca22057c0298321d8ad84
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -108,17 +108,24 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (dma) // Transport 0 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -128,35 +135,39 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (3), .NPORTS (3),
.CHDR_WIDTHS ({EP1_W, EP0_W, DMA_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 3'b111,
3'b111,
3'b111 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (1), .NPORTS_MGMT (1),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -183,26 +194,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384; localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -210,7 +223,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -252,26 +265,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384; localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -279,7 +294,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -404,15 +419,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -437,11 +452,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/e31x/e310_rfnoc_image_core.vh
+1 -3
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@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:33.840276
// Source: e310_rfnoc_image_core.yml // Source: e310_rfnoc_image_core.yml
// Source SHA256: 8e0bdf84e7b65cbc1ad575d1d0a2fdcc33632fe69e8ca22057c0298321d8ad84
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/e320/e320_rfnoc_image_core.v
+158 -131
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@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,17 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:33.413161
// Source: e320_rfnoc_image_core.yml // Source: e320_rfnoc_image_core.yml
// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -108,26 +109,37 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth) // Transport 0 (eth)
input wire [CHDR_W-1:0] s_eth_tdata, input wire [PORT_W-1:0] s_eth_tdata,
input wire s_eth_tlast, input wire s_eth_tlast,
input wire s_eth_tvalid, input wire s_eth_tvalid,
output wire s_eth_tready, output wire s_eth_tready,
output wire [CHDR_W-1:0] m_eth_tdata, output wire [PORT_W-1:0] m_eth_tdata,
output wire m_eth_tlast, output wire m_eth_tlast,
output wire m_eth_tvalid, output wire m_eth_tvalid,
input wire m_eth_tready, input wire m_eth_tready,
// Transport 1 (dma) // Transport 1 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -137,51 +149,58 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (6), .NPORTS (6),
.CHDR_WIDTHS ({EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 6'b111111,
6'b111111,
6'b111111,
6'b111111,
6'b111110,
6'b111101 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (2), .NPORTS_MGMT (2),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -208,26 +227,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768; localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -235,7 +256,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -277,26 +298,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768; localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -304,7 +327,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -346,26 +369,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 8192; localparam REQ_BUFF_SIZE_EP2 = 8192;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -373,7 +398,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -415,26 +440,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 8192; localparam REQ_BUFF_SIZE_EP3 = 8192;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -442,7 +469,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -579,23 +606,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid;
wire s_duc0_in_1_tready, s_duc0_in_0_tready; wire s_duc0_in_1_tready, s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ;
wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ;
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -624,23 +651,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -669,15 +696,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -702,11 +729,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -752,15 +779,15 @@ module rfnoc_image_core #(
// fifo0 // fifo0
//----------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; wire s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_1_tready, s_fifo0_in_0_tready; wire s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [CHDR_W-1:0] m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; wire m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
@@ -811,7 +838,7 @@ module rfnoc_image_core #(
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.MEM_DATA_W (64), .MEM_DATA_W (64),
@@ -820,7 +847,7 @@ module rfnoc_image_core #(
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF}), .FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF}),
.IN_FIFO_SIZE (), .IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (), .OUT_FIFO_SIZE (),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_fifo0_3 ( ) b_fifo0_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/e320/e320_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:33.447436
// Source: e320_rfnoc_image_core.yml // Source: e320_rfnoc_image_core.yml
// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/n3xx/n300_bist_image_core.v
+140 -111
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:29.701839
// Source: n300_bist_image_core.yml // Source: n300_bist_image_core.yml
// Source SHA256: 6c4216a9a0a6064008b2aa7fc1c4c0d22820570c7c1275bab8fefaacd952f6b7
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -108,35 +110,46 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma) // Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -146,51 +159,59 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (7), .NPORTS (7),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 7'b1111111,
7'b1111111,
7'b1111111,
7'b1111111,
7'b1111100,
7'b1111010,
7'b1111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -217,26 +238,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384; localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -244,7 +267,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -286,26 +309,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384; localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -313,7 +338,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -355,26 +380,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 16384; localparam REQ_BUFF_SIZE_EP4 = 16384;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -382,7 +409,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -424,26 +451,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 16384; localparam REQ_BUFF_SIZE_EP5 = 16384;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -451,7 +480,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -580,15 +609,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -613,11 +642,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -663,15 +692,15 @@ module rfnoc_image_core #(
// fifo0 // fifo0
//----------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
@@ -722,7 +751,7 @@ module rfnoc_image_core #(
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
@@ -731,7 +760,7 @@ module rfnoc_image_core #(
.MEM_CLK_RATE (303819444), .MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (), .IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (), .OUT_FIFO_SIZE (),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_fifo0_1 ( ) b_fifo0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/n3xx/n300_bist_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:29.736285
// Source: n300_bist_image_core.yml // Source: n300_bist_image_core.yml
// Source SHA256: 6c4216a9a0a6064008b2aa7fc1c4c0d22820570c7c1275bab8fefaacd952f6b7
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/n3xx/n300_rfnoc_image_core.v
+162 -133
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:30.938217
// Source: n300_rfnoc_image_core.yml // Source: n300_rfnoc_image_core.yml
// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -108,35 +110,46 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma) // Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -146,51 +159,59 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (7), .NPORTS (7),
.CHDR_WIDTHS ({EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 7'b1111111,
7'b1111111,
7'b1111111,
7'b1111111,
7'b1111100,
7'b1111010,
7'b1111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -217,26 +238,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768; localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -244,7 +267,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -286,26 +309,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768; localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -313,7 +338,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -355,26 +380,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 4096; localparam REQ_BUFF_SIZE_EP2 = 4096;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -382,7 +409,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -424,26 +451,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 4096; localparam REQ_BUFF_SIZE_EP3 = 4096;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -451,7 +480,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -588,23 +617,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid;
wire s_duc0_in_1_tready, s_duc0_in_0_tready; wire s_duc0_in_1_tready, s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ;
wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ;
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -633,23 +662,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -678,15 +707,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -711,11 +740,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -761,15 +790,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -820,11 +849,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_3 ( ) b_replay0_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/n3xx/n300_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:30.972437
// Source: n300_rfnoc_image_core.yml // Source: n300_rfnoc_image_core.yml
// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/n3xx/n310_bist_image_core.v
+199 -160
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:30.114198
// Source: n310_bist_image_core.yml // Source: n310_bist_image_core.yml
// Source SHA256: 3f293528e8ab71c93391297481f80833451770735ad8ce695190335ef4457fb4
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -126,35 +128,50 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma) // Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -164,67 +181,77 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (9), .NPORTS (9),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111100,
9'b111111010,
9'b111111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -251,26 +278,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384; localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -278,7 +307,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -320,26 +349,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384; localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -347,7 +378,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -389,26 +420,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 16384; localparam REQ_BUFF_SIZE_EP2 = 16384;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -416,7 +449,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -458,26 +491,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 16384; localparam REQ_BUFF_SIZE_EP3 = 16384;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -485,7 +520,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -527,26 +562,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 16384; localparam REQ_BUFF_SIZE_EP4 = 16384;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -554,7 +591,7 @@ module rfnoc_image_core #(
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -596,26 +633,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 16384; localparam REQ_BUFF_SIZE_EP5 = 16384;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -623,7 +662,7 @@ module rfnoc_image_core #(
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -756,15 +795,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -789,11 +828,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -839,15 +878,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -872,11 +911,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_1 ( ) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -922,15 +961,15 @@ module rfnoc_image_core #(
// fifo0 // fifo0
//----------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
@@ -981,7 +1020,7 @@ module rfnoc_image_core #(
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
@@ -990,7 +1029,7 @@ module rfnoc_image_core #(
.MEM_CLK_RATE (303819444), .MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (), .IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (), .OUT_FIFO_SIZE (),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_fifo0_2 ( ) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/n3xx/n310_bist_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:30.148839
// Source: n310_bist_image_core.yml // Source: n310_bist_image_core.yml
// Source SHA256: 3f293528e8ab71c93391297481f80833451770735ad8ce695190335ef4457fb4
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/n3xx/n310_rfnoc_image_core.v
+291 -242
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:31.355138
// Source: n310_rfnoc_image_core.yml // Source: n310_rfnoc_image_core.yml
// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -126,35 +128,54 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma) // Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
localparam EP6_W = 64;
localparam EP6_MTU = BYTE_MTU - $clog2(EP6_W/8);
localparam EP7_W = 64;
localparam EP7_MTU = BYTE_MTU - $clog2(EP7_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -164,83 +185,95 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep6_tdata ; wire [PORT_W-1:0] xb_to_ep6_tdata ;
wire xb_to_ep6_tlast ; wire xb_to_ep6_tlast ;
wire xb_to_ep6_tvalid; wire xb_to_ep6_tvalid;
wire xb_to_ep6_tready; wire xb_to_ep6_tready;
wire [CHDR_W-1:0] ep6_to_xb_tdata ; wire [PORT_W-1:0] ep6_to_xb_tdata ;
wire ep6_to_xb_tlast ; wire ep6_to_xb_tlast ;
wire ep6_to_xb_tvalid; wire ep6_to_xb_tvalid;
wire ep6_to_xb_tready; wire ep6_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep7_tdata ; wire [PORT_W-1:0] xb_to_ep7_tdata ;
wire xb_to_ep7_tlast ; wire xb_to_ep7_tlast ;
wire xb_to_ep7_tvalid; wire xb_to_ep7_tvalid;
wire xb_to_ep7_tready; wire xb_to_ep7_tready;
wire [CHDR_W-1:0] ep7_to_xb_tdata ; wire [PORT_W-1:0] ep7_to_xb_tdata ;
wire ep7_to_xb_tlast ; wire ep7_to_xb_tlast ;
wire ep7_to_xb_tvalid; wire ep7_to_xb_tvalid;
wire ep7_to_xb_tready; wire ep7_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (11), .NPORTS (11),
.CHDR_WIDTHS ({EP7_W, EP6_W, EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 11'b11111111111,
11'b11111111111,
11'b11111111111,
11'b11111111111,
11'b11111111111,
11'b11111111111,
11'b11111111111,
11'b11111111111,
11'b11111111100,
11'b11111111010,
11'b11111111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -267,26 +300,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768; localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -294,7 +329,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -336,26 +371,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768; localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -363,7 +400,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -405,26 +442,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 32768; localparam REQ_BUFF_SIZE_EP2 = 32768;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -432,7 +471,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -474,26 +513,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 32768; localparam REQ_BUFF_SIZE_EP3 = 32768;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -501,7 +542,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -543,26 +584,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096; localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -570,7 +613,7 @@ module rfnoc_image_core #(
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -612,26 +655,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096; localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -639,7 +684,7 @@ module rfnoc_image_core #(
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -681,26 +726,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP6 = 4096; localparam REQ_BUFF_SIZE_EP6 = 4096;
localparam INGRESS_BUFF_SIZE_EP6 = localparam INGRESS_BUFF_SIZE_EP6 =
REQ_BUFF_SIZE_EP6 == 0 ? 5 : REQ_BUFF_SIZE_EP6 == 0 ? 5 :
REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP6 < 2*(2**EP6_MTU) ? EP6_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP6); $clog2(REQ_BUFF_SIZE_EP6);
wire [CHDR_W-1:0] m_ep6_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep6_out0_tdata;
wire m_ep6_out0_tlast; wire m_ep6_out0_tlast;
wire m_ep6_out0_tvalid; wire m_ep6_out0_tvalid;
wire m_ep6_out0_tready; wire m_ep6_out0_tready;
wire [CHDR_W-1:0] s_ep6_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep6_in0_tdata;
wire s_ep6_in0_tlast; wire s_ep6_in0_tlast;
wire s_ep6_in0_tvalid; wire s_ep6_in0_tvalid;
wire s_ep6_in0_tready; wire s_ep6_in0_tready;
wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata; wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata;
wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast; wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast;
wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid; wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid;
wire m_ep6_ctrl_tready, s_ep6_ctrl_tready; wire m_ep6_ctrl_tready, s_ep6_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP6_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -708,7 +755,7 @@ module rfnoc_image_core #(
.INST_NUM (6), .INST_NUM (6),
.CTRL_XBAR_PORT (7), .CTRL_XBAR_PORT (7),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6),
.MTU (MTU), .MTU (EP6_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep6_i ( ) ep6_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -750,26 +797,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP7 = 4096; localparam REQ_BUFF_SIZE_EP7 = 4096;
localparam INGRESS_BUFF_SIZE_EP7 = localparam INGRESS_BUFF_SIZE_EP7 =
REQ_BUFF_SIZE_EP7 == 0 ? 5 : REQ_BUFF_SIZE_EP7 == 0 ? 5 :
REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP7 < 2*(2**EP7_MTU) ? EP7_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP7); $clog2(REQ_BUFF_SIZE_EP7);
wire [CHDR_W-1:0] m_ep7_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep7_out0_tdata;
wire m_ep7_out0_tlast; wire m_ep7_out0_tlast;
wire m_ep7_out0_tvalid; wire m_ep7_out0_tvalid;
wire m_ep7_out0_tready; wire m_ep7_out0_tready;
wire [CHDR_W-1:0] s_ep7_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep7_in0_tdata;
wire s_ep7_in0_tlast; wire s_ep7_in0_tlast;
wire s_ep7_in0_tvalid; wire s_ep7_in0_tvalid;
wire s_ep7_in0_tready; wire s_ep7_in0_tready;
wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata; wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata;
wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast; wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast;
wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid; wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid;
wire m_ep7_ctrl_tready, s_ep7_ctrl_tready; wire m_ep7_ctrl_tready, s_ep7_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP7_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -777,7 +826,7 @@ module rfnoc_image_core #(
.INST_NUM (7), .INST_NUM (7),
.CTRL_XBAR_PORT (8), .CTRL_XBAR_PORT (8),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7),
.MTU (MTU), .MTU (EP7_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep7_i ( ) ep7_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -926,23 +975,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid;
wire s_duc0_in_1_tready, s_duc0_in_0_tready; wire s_duc0_in_1_tready, s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ;
wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ;
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -971,23 +1020,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1016,15 +1065,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -1049,11 +1098,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1099,23 +1148,23 @@ module rfnoc_image_core #(
// duc1 // duc1
//----------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ;
wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ; wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ;
wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid; wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid;
wire s_duc1_in_1_tready, s_duc1_in_0_tready; wire s_duc1_in_1_tready, s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ;
wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ; wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ;
wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid;
wire m_duc1_out_1_tready, m_duc1_out_0_tready; wire m_duc1_out_1_tready, m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc1_3 ( ) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1144,23 +1193,23 @@ module rfnoc_image_core #(
// ddc1 // ddc1
//----------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc1_4 ( ) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1189,15 +1238,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1222,11 +1271,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_5 ( ) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1272,15 +1321,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -1331,11 +1380,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_6 ( ) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/n3xx/n310_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:31.389520
// Source: n310_rfnoc_image_core.yml // Source: n310_rfnoc_image_core.yml
// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/n3xx/n320_bist_image_core.v
+151 -122
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:30.534235
// Source: n320_bist_image_core.yml // Source: n320_bist_image_core.yml
// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -126,35 +128,46 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma) // Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -164,51 +177,59 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (7), .NPORTS (7),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 7'b1111111,
7'b1111111,
7'b1111111,
7'b1111111,
7'b1111100,
7'b1111010,
7'b1111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -235,26 +256,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768; localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -262,7 +285,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -304,26 +327,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768; localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -331,7 +356,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -373,26 +398,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 32768; localparam REQ_BUFF_SIZE_EP4 = 32768;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -400,7 +427,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -442,26 +469,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 32768; localparam REQ_BUFF_SIZE_EP5 = 32768;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -469,7 +498,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -602,15 +631,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ; wire s_radio0_in_0_tlast ;
wire s_radio0_in_0_tvalid; wire s_radio0_in_0_tvalid;
wire s_radio0_in_0_tready; wire s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ;
wire m_radio0_out_0_tlast ; wire m_radio0_out_0_tlast ;
wire m_radio0_out_0_tvalid; wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready; wire m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -635,11 +664,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -685,15 +714,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ; wire s_radio1_in_0_tlast ;
wire s_radio1_in_0_tvalid; wire s_radio1_in_0_tvalid;
wire s_radio1_in_0_tready; wire s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ;
wire m_radio1_out_0_tlast ; wire m_radio1_out_0_tlast ;
wire m_radio1_out_0_tvalid; wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready; wire m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -718,11 +747,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_1 ( ) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -768,15 +797,15 @@ module rfnoc_image_core #(
// fifo0 // fifo0
//----------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
@@ -827,7 +856,7 @@ module rfnoc_image_core #(
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
@@ -836,7 +865,7 @@ module rfnoc_image_core #(
.MEM_CLK_RATE (303819444), .MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (), .IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (), .OUT_FIFO_SIZE (),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_fifo0_2 ( ) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/n3xx/n320_bist_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:30.568990
// Source: n320_bist_image_core.yml // Source: n320_bist_image_core.yml
// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/n3xx/n320_rfnoc_image_core.v
+195 -166
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:31.762363
// Source: n320_rfnoc_image_core.yml // Source: n320_rfnoc_image_core.yml
// Source SHA256: da09e3fb9d6174f301388ddad69e378ce4505b9c9b7f1bc85075880566e98788
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -126,35 +128,46 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma) // Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -164,51 +177,59 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (7), .NPORTS (7),
.CHDR_WIDTHS ({EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 7'b1111111,
7'b1111111,
7'b1111111,
7'b1111111,
7'b1111100,
7'b1111010,
7'b1111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -235,26 +256,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 65536; localparam REQ_BUFF_SIZE_EP0 = 65536;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -262,7 +285,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -304,26 +327,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 65536; localparam REQ_BUFF_SIZE_EP1 = 65536;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -331,7 +356,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -373,26 +398,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 4096; localparam REQ_BUFF_SIZE_EP2 = 4096;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -400,7 +427,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -442,26 +469,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 4096; localparam REQ_BUFF_SIZE_EP3 = 4096;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -469,7 +498,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -618,23 +647,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid; wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready; wire s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ; wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready; wire m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -663,23 +692,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_0_tdata ;
wire s_ddc0_in_0_tlast ; wire s_ddc0_in_0_tlast ;
wire s_ddc0_in_0_tvalid; wire s_ddc0_in_0_tvalid;
wire s_ddc0_in_0_tready; wire s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_0_tdata ;
wire m_ddc0_out_0_tlast ; wire m_ddc0_out_0_tlast ;
wire m_ddc0_out_0_tvalid; wire m_ddc0_out_0_tvalid;
wire m_ddc0_out_0_tready; wire m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -708,15 +737,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ; wire s_radio0_in_0_tlast ;
wire s_radio0_in_0_tvalid; wire s_radio0_in_0_tvalid;
wire s_radio0_in_0_tready; wire s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ;
wire m_radio0_out_0_tlast ; wire m_radio0_out_0_tlast ;
wire m_radio0_out_0_tvalid; wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready; wire m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -741,11 +770,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -791,23 +820,23 @@ module rfnoc_image_core #(
// duc1 // duc1
//----------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid; wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready; wire s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ; wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready; wire m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc1_3 ( ) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -836,23 +865,23 @@ module rfnoc_image_core #(
// ddc1 // ddc1
//----------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc1_in_0_tdata ;
wire s_ddc1_in_0_tlast ; wire s_ddc1_in_0_tlast ;
wire s_ddc1_in_0_tvalid; wire s_ddc1_in_0_tvalid;
wire s_ddc1_in_0_tready; wire s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc1_out_0_tdata ;
wire m_ddc1_out_0_tlast ; wire m_ddc1_out_0_tlast ;
wire m_ddc1_out_0_tvalid; wire m_ddc1_out_0_tvalid;
wire m_ddc1_out_0_tready; wire m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc1_4 ( ) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -881,15 +910,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ; wire s_radio1_in_0_tlast ;
wire s_radio1_in_0_tvalid; wire s_radio1_in_0_tvalid;
wire s_radio1_in_0_tready; wire s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ;
wire m_radio1_out_0_tlast ; wire m_radio1_out_0_tlast ;
wire m_radio1_out_0_tvalid; wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready; wire m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -914,11 +943,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_5 ( ) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -964,15 +993,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -1023,11 +1052,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_6 ( ) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/n3xx/n320_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:31.796221
// Source: n320_rfnoc_image_core.yml // Source: n320_rfnoc_image_core.yml
// Source SHA256: da09e3fb9d6174f301388ddad69e378ce4505b9c9b7f1bc85075880566e98788
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/x300/x300_rfnoc_image_core.v
+243 -204
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:32.588967
// Source: x300_rfnoc_image_core.yml // Source: x300_rfnoc_image_core.yml
// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] PCIE_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -127,35 +129,50 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (pcie) // Transport 2 (pcie)
input wire [CHDR_W-1:0] s_pcie_tdata, input wire [PORT_W-1:0] s_pcie_tdata,
input wire s_pcie_tlast, input wire s_pcie_tlast,
input wire s_pcie_tvalid, input wire s_pcie_tvalid,
output wire s_pcie_tready, output wire s_pcie_tready,
output wire [CHDR_W-1:0] m_pcie_tdata, output wire [PORT_W-1:0] m_pcie_tdata,
output wire m_pcie_tlast, output wire m_pcie_tlast,
output wire m_pcie_tvalid, output wire m_pcie_tvalid,
input wire m_pcie_tready input wire m_pcie_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -165,67 +182,77 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (9), .NPORTS (9),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, PCIE_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111100,
9'b111111010,
9'b111111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -252,26 +279,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768; localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -279,7 +308,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -321,26 +350,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 0; localparam REQ_BUFF_SIZE_EP1 = 0;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -348,7 +379,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -390,26 +421,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 32768; localparam REQ_BUFF_SIZE_EP2 = 32768;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -417,7 +450,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -459,26 +492,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 0; localparam REQ_BUFF_SIZE_EP3 = 0;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -486,7 +521,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -528,26 +563,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096; localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -555,7 +592,7 @@ module rfnoc_image_core #(
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -597,26 +634,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096; localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -624,7 +663,7 @@ module rfnoc_image_core #(
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -773,23 +812,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid; wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready; wire s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ; wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready; wire m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -818,23 +857,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -863,15 +902,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -896,11 +935,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -946,23 +985,23 @@ module rfnoc_image_core #(
// duc1 // duc1
//----------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid; wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready; wire s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ; wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready; wire m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc1_3 ( ) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -991,23 +1030,23 @@ module rfnoc_image_core #(
// ddc1 // ddc1
//----------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc1_4 ( ) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1036,15 +1075,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1069,11 +1108,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_5 ( ) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1119,15 +1158,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -1178,11 +1217,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.MEM_ADDR_W (30), .MEM_ADDR_W (30),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_6 ( ) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x300/x300_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:32.623216
// Source: x300_rfnoc_image_core.yml // Source: x300_rfnoc_image_core.yml
// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/x300/x310_rfnoc_image_core.v
+243 -204
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:33.009325
// Source: x310_rfnoc_image_core.yml // Source: x310_rfnoc_image_core.yml
// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] PCIE_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -127,35 +129,50 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (pcie) // Transport 2 (pcie)
input wire [CHDR_W-1:0] s_pcie_tdata, input wire [PORT_W-1:0] s_pcie_tdata,
input wire s_pcie_tlast, input wire s_pcie_tlast,
input wire s_pcie_tvalid, input wire s_pcie_tvalid,
output wire s_pcie_tready, output wire s_pcie_tready,
output wire [CHDR_W-1:0] m_pcie_tdata, output wire [PORT_W-1:0] m_pcie_tdata,
output wire m_pcie_tlast, output wire m_pcie_tlast,
output wire m_pcie_tvalid, output wire m_pcie_tvalid,
input wire m_pcie_tready input wire m_pcie_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -165,67 +182,77 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (9), .NPORTS (9),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, PCIE_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111100,
9'b111111010,
9'b111111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (3), .NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -252,26 +279,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 65536; localparam REQ_BUFF_SIZE_EP0 = 65536;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -279,7 +308,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -321,26 +350,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 0; localparam REQ_BUFF_SIZE_EP1 = 0;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -348,7 +379,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -390,26 +421,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 65536; localparam REQ_BUFF_SIZE_EP2 = 65536;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -417,7 +450,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -459,26 +492,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 0; localparam REQ_BUFF_SIZE_EP3 = 0;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -486,7 +521,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -528,26 +563,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096; localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -555,7 +592,7 @@ module rfnoc_image_core #(
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -597,26 +634,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096; localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -624,7 +663,7 @@ module rfnoc_image_core #(
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -773,23 +812,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid; wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready; wire s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ; wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready; wire m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -818,23 +857,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -863,15 +902,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -896,11 +935,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -946,23 +985,23 @@ module rfnoc_image_core #(
// duc1 // duc1
//----------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid; wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready; wire s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ; wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready; wire m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1), .NUM_PORTS (1),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc1_3 ( ) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -991,23 +1030,23 @@ module rfnoc_image_core #(
// ddc1 // ddc1
//----------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc1_4 ( ) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1036,15 +1075,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1069,11 +1108,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (1), .NIPC (1),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_5 ( ) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1119,15 +1158,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -1178,11 +1217,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (30), .MEM_ADDR_W (30),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_6 ( ) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x300/x310_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:33.044163
// Source: x310_rfnoc_image_core.yml // Source: x310_rfnoc_image_core.yml
// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/x400/x410_200_rfnoc_image_core.v
+312 -257
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,21 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-04-05T20:50:48.332788 // Source: x410_200_rfnoc_image_core.yml
// Source: ./x410_200_rfnoc_image_core.yml
// Source SHA256: 69661f9e2e1c218f3c199f2c8017b4b83f8b53eb47af157d455e27f719902f6b
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 64, parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] ETH2_W = 64,
parameter [31:0] ETH3_W = 64,
parameter [31:0] ETH4_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -127,62 +132,81 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (eth2) // Transport 2 (eth2)
input wire [CHDR_W-1:0] s_eth2_tdata, input wire [PORT_W-1:0] s_eth2_tdata,
input wire s_eth2_tlast, input wire s_eth2_tlast,
input wire s_eth2_tvalid, input wire s_eth2_tvalid,
output wire s_eth2_tready, output wire s_eth2_tready,
output wire [CHDR_W-1:0] m_eth2_tdata, output wire [PORT_W-1:0] m_eth2_tdata,
output wire m_eth2_tlast, output wire m_eth2_tlast,
output wire m_eth2_tvalid, output wire m_eth2_tvalid,
input wire m_eth2_tready, input wire m_eth2_tready,
// Transport 3 (eth3) // Transport 3 (eth3)
input wire [CHDR_W-1:0] s_eth3_tdata, input wire [PORT_W-1:0] s_eth3_tdata,
input wire s_eth3_tlast, input wire s_eth3_tlast,
input wire s_eth3_tvalid, input wire s_eth3_tvalid,
output wire s_eth3_tready, output wire s_eth3_tready,
output wire [CHDR_W-1:0] m_eth3_tdata, output wire [PORT_W-1:0] m_eth3_tdata,
output wire m_eth3_tlast, output wire m_eth3_tlast,
output wire m_eth3_tvalid, output wire m_eth3_tvalid,
input wire m_eth3_tready, input wire m_eth3_tready,
// Transport 4 (eth4) // Transport 4 (eth4)
input wire [CHDR_W-1:0] s_eth4_tdata, input wire [PORT_W-1:0] s_eth4_tdata,
input wire s_eth4_tlast, input wire s_eth4_tlast,
input wire s_eth4_tvalid, input wire s_eth4_tvalid,
output wire s_eth4_tready, output wire s_eth4_tready,
output wire [CHDR_W-1:0] m_eth4_tdata, output wire [PORT_W-1:0] m_eth4_tdata,
output wire m_eth4_tlast, output wire m_eth4_tlast,
output wire m_eth4_tvalid, output wire m_eth4_tvalid,
input wire m_eth4_tready, input wire m_eth4_tready,
// Transport 5 (dma) // Transport 5 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
localparam EP6_W = 64;
localparam EP6_MTU = BYTE_MTU - $clog2(EP6_W/8);
localparam EP7_W = 64;
localparam EP7_MTU = BYTE_MTU - $clog2(EP7_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -192,83 +216,98 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep6_tdata ; wire [PORT_W-1:0] xb_to_ep6_tdata ;
wire xb_to_ep6_tlast ; wire xb_to_ep6_tlast ;
wire xb_to_ep6_tvalid; wire xb_to_ep6_tvalid;
wire xb_to_ep6_tready; wire xb_to_ep6_tready;
wire [CHDR_W-1:0] ep6_to_xb_tdata ; wire [PORT_W-1:0] ep6_to_xb_tdata ;
wire ep6_to_xb_tlast ; wire ep6_to_xb_tlast ;
wire ep6_to_xb_tvalid; wire ep6_to_xb_tvalid;
wire ep6_to_xb_tready; wire ep6_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep7_tdata ; wire [PORT_W-1:0] xb_to_ep7_tdata ;
wire xb_to_ep7_tlast ; wire xb_to_ep7_tlast ;
wire xb_to_ep7_tvalid; wire xb_to_ep7_tvalid;
wire xb_to_ep7_tready; wire xb_to_ep7_tready;
wire [CHDR_W-1:0] ep7_to_xb_tdata ; wire [PORT_W-1:0] ep7_to_xb_tdata ;
wire ep7_to_xb_tlast ; wire ep7_to_xb_tlast ;
wire ep7_to_xb_tvalid; wire ep7_to_xb_tvalid;
wire ep7_to_xb_tready; wire ep7_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (14), .NPORTS (14),
.CHDR_WIDTHS ({EP7_W, EP6_W, EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111100000,
14'b11111111010000,
14'b11111111001000,
14'b11111111000100,
14'b11111111000010,
14'b11111111000001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (6), .NPORTS_MGMT (6),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -293,28 +332,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = (262144)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -322,7 +363,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -362,28 +403,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = (262144)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -391,7 +434,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -431,28 +474,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = (262144)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP2 = 32768;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -460,7 +505,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -500,28 +545,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = (262144)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP3 = 32768;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -529,7 +576,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -569,28 +616,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -598,7 +647,7 @@ module rfnoc_image_core #(
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -638,28 +687,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -667,7 +718,7 @@ module rfnoc_image_core #(
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -707,28 +758,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP6 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP6 = 4096;
localparam INGRESS_BUFF_SIZE_EP6 = localparam INGRESS_BUFF_SIZE_EP6 =
REQ_BUFF_SIZE_EP6 == 0 ? 5 : REQ_BUFF_SIZE_EP6 == 0 ? 5 :
REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP6 < 2*(2**EP6_MTU) ? EP6_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP6); $clog2(REQ_BUFF_SIZE_EP6);
wire [CHDR_W-1:0] m_ep6_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep6_out0_tdata;
wire m_ep6_out0_tlast; wire m_ep6_out0_tlast;
wire m_ep6_out0_tvalid; wire m_ep6_out0_tvalid;
wire m_ep6_out0_tready; wire m_ep6_out0_tready;
wire [CHDR_W-1:0] s_ep6_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep6_in0_tdata;
wire s_ep6_in0_tlast; wire s_ep6_in0_tlast;
wire s_ep6_in0_tvalid; wire s_ep6_in0_tvalid;
wire s_ep6_in0_tready; wire s_ep6_in0_tready;
wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata; wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata;
wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast; wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast;
wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid; wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid;
wire m_ep6_ctrl_tready, s_ep6_ctrl_tready; wire m_ep6_ctrl_tready, s_ep6_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP6_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -736,7 +789,7 @@ module rfnoc_image_core #(
.INST_NUM (6), .INST_NUM (6),
.CTRL_XBAR_PORT (7), .CTRL_XBAR_PORT (7),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6),
.MTU (MTU), .MTU (EP6_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep6_i ( ) ep6_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -776,28 +829,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP7 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP7 = 4096;
localparam INGRESS_BUFF_SIZE_EP7 = localparam INGRESS_BUFF_SIZE_EP7 =
REQ_BUFF_SIZE_EP7 == 0 ? 5 : REQ_BUFF_SIZE_EP7 == 0 ? 5 :
REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP7 < 2*(2**EP7_MTU) ? EP7_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP7); $clog2(REQ_BUFF_SIZE_EP7);
wire [CHDR_W-1:0] m_ep7_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep7_out0_tdata;
wire m_ep7_out0_tlast; wire m_ep7_out0_tlast;
wire m_ep7_out0_tvalid; wire m_ep7_out0_tvalid;
wire m_ep7_out0_tready; wire m_ep7_out0_tready;
wire [CHDR_W-1:0] s_ep7_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep7_in0_tdata;
wire s_ep7_in0_tlast; wire s_ep7_in0_tlast;
wire s_ep7_in0_tvalid; wire s_ep7_in0_tvalid;
wire s_ep7_in0_tready; wire s_ep7_in0_tready;
wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata; wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata;
wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast; wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast;
wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid; wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid;
wire m_ep7_ctrl_tready, s_ep7_ctrl_tready; wire m_ep7_ctrl_tready, s_ep7_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP7_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -805,7 +860,7 @@ module rfnoc_image_core #(
.INST_NUM (7), .INST_NUM (7),
.CTRL_XBAR_PORT (8), .CTRL_XBAR_PORT (8),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7),
.MTU (MTU), .MTU (EP7_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep7_i ( ) ep7_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -954,23 +1009,23 @@ module rfnoc_image_core #(
// duc0 // duc0
//----------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid;
wire s_duc0_in_1_tready, s_duc0_in_0_tready; wire s_duc0_in_1_tready, s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ;
wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ;
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc0_0 ( ) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -999,23 +1054,23 @@ module rfnoc_image_core #(
// ddc0 // ddc0
//----------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc0_1 ( ) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1044,15 +1099,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -1077,11 +1132,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (RADIO_NIPC), .NIPC (RADIO_NIPC),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_2 ( ) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1127,23 +1182,23 @@ module rfnoc_image_core #(
// duc1 // duc1
//----------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ;
wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ; wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ;
wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid; wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid;
wire s_duc1_in_1_tready, s_duc1_in_0_tready; wire s_duc1_in_1_tready, s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ;
wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ; wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ;
wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid;
wire m_duc1_out_1_tready, m_duc1_out_0_tready; wire m_duc1_out_1_tready, m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_INTERP (255), .CIC_MAX_INTERP (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_duc1_3 ( ) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1172,23 +1227,23 @@ module rfnoc_image_core #(
// ddc1 // ddc1
//----------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NUM_HB (3), .NUM_HB (3),
.CIC_MAX_DECIM (255), .CIC_MAX_DECIM (255),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_ddc1_4 ( ) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1217,15 +1272,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1250,11 +1305,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (RADIO_NIPC), .NIPC (RADIO_NIPC),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_5 ( ) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1300,15 +1355,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -1359,11 +1414,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (32), .MEM_ADDR_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_6 ( ) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x400/x410_200_rfnoc_image_core.vh
+2 -4
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-04-05T20:50:48.367079 // Source: x410_200_rfnoc_image_core.yml
// Source: ./x410_200_rfnoc_image_core.yml
// Source SHA256: 69661f9e2e1c218f3c199f2c8017b4b83f8b53eb47af157d455e27f719902f6b
// //
`define CHDR_WIDTH 64 `define CHDR_WIDTH 64
top/x400/x410_400_128_rfnoc_image_core.v
+267 -212
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,21 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:35.478639
// Source: x410_400_128_rfnoc_image_core.yml // Source: x410_400_128_rfnoc_image_core.yml
// Source SHA256: 0e1aea15a9108fa6fbc86d91a7ee9930440a03c66e96bcd86c179ed5b6da5d53
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 128, parameter [31:0] CHDR_W = 128,
parameter [31:0] PORT_W = 128,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] ETH2_W = 64,
parameter [31:0] ETH3_W = 64,
parameter [31:0] ETH4_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -127,62 +132,81 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (eth2) // Transport 2 (eth2)
input wire [CHDR_W-1:0] s_eth2_tdata, input wire [PORT_W-1:0] s_eth2_tdata,
input wire s_eth2_tlast, input wire s_eth2_tlast,
input wire s_eth2_tvalid, input wire s_eth2_tvalid,
output wire s_eth2_tready, output wire s_eth2_tready,
output wire [CHDR_W-1:0] m_eth2_tdata, output wire [PORT_W-1:0] m_eth2_tdata,
output wire m_eth2_tlast, output wire m_eth2_tlast,
output wire m_eth2_tvalid, output wire m_eth2_tvalid,
input wire m_eth2_tready, input wire m_eth2_tready,
// Transport 3 (eth3) // Transport 3 (eth3)
input wire [CHDR_W-1:0] s_eth3_tdata, input wire [PORT_W-1:0] s_eth3_tdata,
input wire s_eth3_tlast, input wire s_eth3_tlast,
input wire s_eth3_tvalid, input wire s_eth3_tvalid,
output wire s_eth3_tready, output wire s_eth3_tready,
output wire [CHDR_W-1:0] m_eth3_tdata, output wire [PORT_W-1:0] m_eth3_tdata,
output wire m_eth3_tlast, output wire m_eth3_tlast,
output wire m_eth3_tvalid, output wire m_eth3_tvalid,
input wire m_eth3_tready, input wire m_eth3_tready,
// Transport 4 (eth4) // Transport 4 (eth4)
input wire [CHDR_W-1:0] s_eth4_tdata, input wire [PORT_W-1:0] s_eth4_tdata,
input wire s_eth4_tlast, input wire s_eth4_tlast,
input wire s_eth4_tvalid, input wire s_eth4_tvalid,
output wire s_eth4_tready, output wire s_eth4_tready,
output wire [CHDR_W-1:0] m_eth4_tdata, output wire [PORT_W-1:0] m_eth4_tdata,
output wire m_eth4_tlast, output wire m_eth4_tlast,
output wire m_eth4_tvalid, output wire m_eth4_tvalid,
input wire m_eth4_tready, input wire m_eth4_tready,
// Transport 5 (dma) // Transport 5 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 128;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 128;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 128;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 128;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 128;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 128;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 128;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
localparam EP6_W = 128;
localparam EP6_MTU = BYTE_MTU - $clog2(EP6_W/8);
localparam EP7_W = 128;
localparam EP7_MTU = BYTE_MTU - $clog2(EP7_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -192,83 +216,98 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ; wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ; wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid; wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready; wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ; wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ; wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid; wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready; wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ; wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ; wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid; wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready; wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ; wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ; wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid; wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready; wire ep5_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep6_tdata ; wire [PORT_W-1:0] xb_to_ep6_tdata ;
wire xb_to_ep6_tlast ; wire xb_to_ep6_tlast ;
wire xb_to_ep6_tvalid; wire xb_to_ep6_tvalid;
wire xb_to_ep6_tready; wire xb_to_ep6_tready;
wire [CHDR_W-1:0] ep6_to_xb_tdata ; wire [PORT_W-1:0] ep6_to_xb_tdata ;
wire ep6_to_xb_tlast ; wire ep6_to_xb_tlast ;
wire ep6_to_xb_tvalid; wire ep6_to_xb_tvalid;
wire ep6_to_xb_tready; wire ep6_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep7_tdata ; wire [PORT_W-1:0] xb_to_ep7_tdata ;
wire xb_to_ep7_tlast ; wire xb_to_ep7_tlast ;
wire xb_to_ep7_tvalid; wire xb_to_ep7_tvalid;
wire xb_to_ep7_tready; wire xb_to_ep7_tready;
wire [CHDR_W-1:0] ep7_to_xb_tdata ; wire [PORT_W-1:0] ep7_to_xb_tdata ;
wire ep7_to_xb_tlast ; wire ep7_to_xb_tlast ;
wire ep7_to_xb_tvalid; wire ep7_to_xb_tvalid;
wire ep7_to_xb_tready; wire ep7_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (14), .NPORTS (14),
.CHDR_WIDTHS ({EP7_W, EP6_W, EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111111111,
14'b11111111100000,
14'b11111111010000,
14'b11111111001000,
14'b11111111000100,
14'b11111111000010,
14'b11111111000001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (6), .NPORTS_MGMT (6),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -293,28 +332,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP0 = 2048;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -322,7 +363,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -362,28 +403,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP1 = 2048;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -391,7 +434,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -431,28 +474,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP2 = 2048;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -460,7 +505,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -500,28 +545,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP3 = 2048;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -529,7 +576,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -569,28 +616,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP4 = 2048;
localparam INGRESS_BUFF_SIZE_EP4 = localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4); $clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready; wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast; wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid; wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready; wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -598,7 +647,7 @@ module rfnoc_image_core #(
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (EP4_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -638,28 +687,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP5 = 2048;
localparam INGRESS_BUFF_SIZE_EP5 = localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5); $clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready; wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast; wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid; wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready; wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -667,7 +718,7 @@ module rfnoc_image_core #(
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (EP5_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -707,28 +758,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP6 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP6 = 2048;
localparam INGRESS_BUFF_SIZE_EP6 = localparam INGRESS_BUFF_SIZE_EP6 =
REQ_BUFF_SIZE_EP6 == 0 ? 5 : REQ_BUFF_SIZE_EP6 == 0 ? 5 :
REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP6 < 2*(2**EP6_MTU) ? EP6_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP6); $clog2(REQ_BUFF_SIZE_EP6);
wire [CHDR_W-1:0] m_ep6_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep6_out0_tdata;
wire m_ep6_out0_tlast; wire m_ep6_out0_tlast;
wire m_ep6_out0_tvalid; wire m_ep6_out0_tvalid;
wire m_ep6_out0_tready; wire m_ep6_out0_tready;
wire [CHDR_W-1:0] s_ep6_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep6_in0_tdata;
wire s_ep6_in0_tlast; wire s_ep6_in0_tlast;
wire s_ep6_in0_tvalid; wire s_ep6_in0_tvalid;
wire s_ep6_in0_tready; wire s_ep6_in0_tready;
wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata; wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata;
wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast; wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast;
wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid; wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid;
wire m_ep6_ctrl_tready, s_ep6_ctrl_tready; wire m_ep6_ctrl_tready, s_ep6_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP6_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -736,7 +789,7 @@ module rfnoc_image_core #(
.INST_NUM (6), .INST_NUM (6),
.CTRL_XBAR_PORT (7), .CTRL_XBAR_PORT (7),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6),
.MTU (MTU), .MTU (EP6_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep6_i ( ) ep6_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -776,28 +829,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP7 = (32768)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP7 = 2048;
localparam INGRESS_BUFF_SIZE_EP7 = localparam INGRESS_BUFF_SIZE_EP7 =
REQ_BUFF_SIZE_EP7 == 0 ? 5 : REQ_BUFF_SIZE_EP7 == 0 ? 5 :
REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP7 < 2*(2**EP7_MTU) ? EP7_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP7); $clog2(REQ_BUFF_SIZE_EP7);
wire [CHDR_W-1:0] m_ep7_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep7_out0_tdata;
wire m_ep7_out0_tlast; wire m_ep7_out0_tlast;
wire m_ep7_out0_tvalid; wire m_ep7_out0_tvalid;
wire m_ep7_out0_tready; wire m_ep7_out0_tready;
wire [CHDR_W-1:0] s_ep7_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep7_in0_tdata;
wire s_ep7_in0_tlast; wire s_ep7_in0_tlast;
wire s_ep7_in0_tvalid; wire s_ep7_in0_tvalid;
wire s_ep7_in0_tready; wire s_ep7_in0_tready;
wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata; wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata;
wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast; wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast;
wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid; wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid;
wire m_ep7_ctrl_tready, s_ep7_ctrl_tready; wire m_ep7_ctrl_tready, s_ep7_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP7_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -805,7 +860,7 @@ module rfnoc_image_core #(
.INST_NUM (7), .INST_NUM (7),
.CTRL_XBAR_PORT (8), .CTRL_XBAR_PORT (8),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7),
.MTU (MTU), .MTU (EP7_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep7_i ( ) ep7_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -938,15 +993,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -971,11 +1026,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (RADIO_NIPC), .NIPC (RADIO_NIPC),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1021,15 +1076,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1054,11 +1109,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (RADIO_NIPC), .NIPC (RADIO_NIPC),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_1 ( ) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1104,15 +1159,15 @@ module rfnoc_image_core #(
// replay0 // replay0
//----------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready; wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ; wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 0:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
@@ -1163,11 +1218,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (4), .THIS_PORTID (4),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (128), .MEM_DATA_W (128),
.MEM_ADDR_W (32), .MEM_ADDR_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_replay0_2 ( ) b_replay0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x400/x410_400_128_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:35.513269
// Source: x410_400_128_rfnoc_image_core.yml // Source: x410_400_128_rfnoc_image_core.yml
// Source SHA256: 0e1aea15a9108fa6fbc86d91a7ee9930440a03c66e96bcd86c179ed5b6da5d53
// //
`define CHDR_WIDTH 128 `define CHDR_WIDTH 128
top/x400/x410_400_rfnoc_image_core.v
+156 -121
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,16 +13,21 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:35.062926
// Source: x410_400_rfnoc_image_core.yml // Source: x410_400_rfnoc_image_core.yml
// Source SHA256: 58e375a5b646df42d81e3af066727c562580c7d98df5eb361163e0924463a466
// //
`default_nettype none `default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter CHDR_W = 512, parameter [31:0] CHDR_W = 512,
parameter [31:0] PORT_W = 512,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] ETH2_W = 64,
parameter [31:0] ETH3_W = 64,
parameter [31:0] ETH4_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10, parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0}, parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1 parameter RADIO_NIPC = 1
@@ -127,62 +132,73 @@ module rfnoc_image_core #(
// Transport Adapters /////////////// // Transport Adapters ///////////////
// Transport 0 (eth0) // Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata, input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata, output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1) // Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata, input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata, output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (eth2) // Transport 2 (eth2)
input wire [CHDR_W-1:0] s_eth2_tdata, input wire [PORT_W-1:0] s_eth2_tdata,
input wire s_eth2_tlast, input wire s_eth2_tlast,
input wire s_eth2_tvalid, input wire s_eth2_tvalid,
output wire s_eth2_tready, output wire s_eth2_tready,
output wire [CHDR_W-1:0] m_eth2_tdata, output wire [PORT_W-1:0] m_eth2_tdata,
output wire m_eth2_tlast, output wire m_eth2_tlast,
output wire m_eth2_tvalid, output wire m_eth2_tvalid,
input wire m_eth2_tready, input wire m_eth2_tready,
// Transport 3 (eth3) // Transport 3 (eth3)
input wire [CHDR_W-1:0] s_eth3_tdata, input wire [PORT_W-1:0] s_eth3_tdata,
input wire s_eth3_tlast, input wire s_eth3_tlast,
input wire s_eth3_tvalid, input wire s_eth3_tvalid,
output wire s_eth3_tready, output wire s_eth3_tready,
output wire [CHDR_W-1:0] m_eth3_tdata, output wire [PORT_W-1:0] m_eth3_tdata,
output wire m_eth3_tlast, output wire m_eth3_tlast,
output wire m_eth3_tvalid, output wire m_eth3_tvalid,
input wire m_eth3_tready, input wire m_eth3_tready,
// Transport 4 (eth4) // Transport 4 (eth4)
input wire [CHDR_W-1:0] s_eth4_tdata, input wire [PORT_W-1:0] s_eth4_tdata,
input wire s_eth4_tlast, input wire s_eth4_tlast,
input wire s_eth4_tvalid, input wire s_eth4_tvalid,
output wire s_eth4_tready, output wire s_eth4_tready,
output wire [CHDR_W-1:0] m_eth4_tdata, output wire [PORT_W-1:0] m_eth4_tdata,
output wire m_eth4_tlast, output wire m_eth4_tlast,
output wire m_eth4_tvalid, output wire m_eth4_tvalid,
input wire m_eth4_tready, input wire m_eth4_tready,
// Transport 5 (dma) // Transport 5 (dma)
input wire [CHDR_W-1:0] s_dma_tdata, input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata, output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 512;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 512;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 512;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 512;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 512;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -192,51 +208,62 @@ module rfnoc_image_core #(
// CHDR Crossbar // CHDR Crossbar
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready; wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ; wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ; wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid; wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready; wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ; wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ; wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid; wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready; wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ; wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ; wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid; wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready; wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ; wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ; wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid; wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready; wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ; wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ; wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid; wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready; wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ; wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ; wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid; wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready; wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ; wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ; wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid; wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready; wire ep3_to_xb_tready;
chdr_crossbar_nxn #( chdr_crossbar_nxn #(
.CHDR_W (CHDR_W), .PORT_W (PORT_W),
.NPORTS (10), .NPORTS (10),
.CHDR_WIDTHS ({EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0), .DEFAULT_PORT (0),
.MTU (MTU), .ROUTES ({ 10'b1111111111,
10'b1111111111,
10'b1111111111,
10'b1111111111,
10'b1111100000,
10'b1111010000,
10'b1111001000,
10'b1111000100,
10'b1111000010,
10'b1111000001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6), .ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"), .MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"), .OPTIMIZE ("AREA"),
.NPORTS_MGMT (6), .NPORTS_MGMT (6),
.EXT_RTCFG_PORT (0), .EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER) .PROTOVER (PROTOVER)
) chdr_xb_i ( ) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
@@ -261,28 +288,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = (524288)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP0 = 8192;
localparam INGRESS_BUFF_SIZE_EP0 = localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0); $clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid; wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready; wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1), .AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -290,7 +319,7 @@ module rfnoc_image_core #(
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (EP0_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -330,28 +359,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = (524288)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP1 = 8192;
localparam INGRESS_BUFF_SIZE_EP1 = localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1); $clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready; wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -359,7 +390,7 @@ module rfnoc_image_core #(
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (EP1_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -399,28 +430,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = (524288)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP2 = 8192;
localparam INGRESS_BUFF_SIZE_EP2 = localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2); $clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready; wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast; wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid; wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready; wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -428,7 +461,7 @@ module rfnoc_image_core #(
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (EP2_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -468,28 +501,30 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size. // If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets. // Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = (524288)/(CHDR_W/8); localparam REQ_BUFF_SIZE_EP3 = 8192;
localparam INGRESS_BUFF_SIZE_EP3 = localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3); $clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready; wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata; wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast; wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid; wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready; wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #( chdr_stream_endpoint #(
.DEVICE_FAMILY ("ULTRASCALE"),
.PROTOVER (PROTOVER), .PROTOVER (PROTOVER),
.CHDR_W (CHDR_W), .CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0), .AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1), .AXIS_DATA_EN (1),
.NUM_DATA_I (1), .NUM_DATA_I (1),
@@ -497,7 +532,7 @@ module rfnoc_image_core #(
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (EP3_MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -626,15 +661,15 @@ module rfnoc_image_core #(
// radio0 // radio0
//----------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready; wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -659,11 +694,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (RADIO_NIPC), .NIPC (RADIO_NIPC),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -709,15 +744,15 @@ module rfnoc_image_core #(
// radio1 // radio1
//----------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready; wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -742,11 +777,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2), .NUM_PORTS (2),
.NIPC (RADIO_NIPC), .NIPC (RADIO_NIPC),
.ITEM_W (32), .ITEM_W (32),
.MTU (MTU) .MTU (BLOCK_MTU)
) b_radio1_1 ( ) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x400/x410_400_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, A National Instruments Brand // Copyright 2023 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2022-03-29T22:54:35.096636
// Source: x410_400_rfnoc_image_core.yml // Source: x410_400_rfnoc_image_core.yml
// Source SHA256: 58e375a5b646df42d81e3af066727c562580c7d98df5eb361163e0924463a466
// //
`define CHDR_WIDTH 512 `define CHDR_WIDTH 512