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fpga: Update all RFNoC image core files

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Original-commit: 0fca5d5ffda1f5f4f7c966c3e5f5200222a5a575
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent fae19151c4
commit aeaf219f77
26 changed files with 2604 additions and 2161 deletions
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top/x300/x300_rfnoc_image_core.v
+243 -204
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-29T22:54:32.588967
// Source: x300_rfnoc_image_core.yml
// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
//
`default_nettype none
module rfnoc_image_core #(
parameter CHDR_W = 64,
parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] PCIE_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
@@ -127,35 +129,50 @@ module rfnoc_image_core #(
// Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast,
input wire s_eth0_tvalid,
output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata,
output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast,
output wire m_eth0_tvalid,
input wire m_eth0_tready,
// Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata,
input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast,
input wire s_eth1_tvalid,
output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata,
output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast,
output wire m_eth1_tvalid,
input wire m_eth1_tready,
// Transport 2 (pcie)
input wire [CHDR_W-1:0] s_pcie_tdata,
input wire [PORT_W-1:0] s_pcie_tdata,
input wire s_pcie_tlast,
input wire s_pcie_tvalid,
output wire s_pcie_tready,
output wire [CHDR_W-1:0] m_pcie_tdata,
output wire [PORT_W-1:0] m_pcie_tdata,
output wire m_pcie_tlast,
output wire m_pcie_tvalid,
input wire m_pcie_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -165,67 +182,77 @@ module rfnoc_image_core #(
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ;
wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ;
wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ;
wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ;
wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ;
wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ;
wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ;
wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ;
wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready;
chdr_crossbar_nxn #(
.CHDR_W (CHDR_W),
.PORT_W (PORT_W),
.NPORTS (9),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, PCIE_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0),
.MTU (MTU),
.ROUTES ({ 9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111100,
9'b111111010,
9'b111111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_xb_i (
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
@@ -252,26 +279,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -279,7 +308,7 @@ module rfnoc_image_core #(
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -321,26 +350,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 0;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -348,7 +379,7 @@ module rfnoc_image_core #(
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -390,26 +421,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 32768;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -417,7 +450,7 @@ module rfnoc_image_core #(
.INST_NUM (2),
.CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU),
.MTU (EP2_MTU),
.REPORT_STRM_ERRS (1)
) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -459,26 +492,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 0;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -486,7 +521,7 @@ module rfnoc_image_core #(
.INST_NUM (3),
.CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU),
.MTU (EP3_MTU),
.REPORT_STRM_ERRS (1)
) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -528,26 +563,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -555,7 +592,7 @@ module rfnoc_image_core #(
.INST_NUM (4),
.CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU),
.MTU (EP4_MTU),
.REPORT_STRM_ERRS (1)
) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -597,26 +634,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -624,7 +663,7 @@ module rfnoc_image_core #(
.INST_NUM (5),
.CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU),
.MTU (EP5_MTU),
.REPORT_STRM_ERRS (1)
) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -773,23 +812,23 @@ module rfnoc_image_core #(
// duc0
//-----------------------------------
wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready;
wire duc0_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NUM_HB (3),
.CIC_MAX_INTERP (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -818,23 +857,23 @@ module rfnoc_image_core #(
// ddc0
//-----------------------------------
wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
wire ddc0_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NUM_HB (3),
.CIC_MAX_DECIM (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -863,15 +902,15 @@ module rfnoc_image_core #(
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -896,11 +935,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -946,23 +985,23 @@ module rfnoc_image_core #(
// duc1
//-----------------------------------
wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready;
wire duc1_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (5),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NUM_HB (3),
.CIC_MAX_INTERP (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -991,23 +1030,23 @@ module rfnoc_image_core #(
// ddc1
//-----------------------------------
wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
wire ddc1_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (6),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NUM_HB (3),
.CIC_MAX_DECIM (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1036,15 +1075,15 @@ module rfnoc_image_core #(
// radio1
//-----------------------------------
wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
wire radio1_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1069,11 +1108,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1119,15 +1158,15 @@ module rfnoc_image_core #(
// replay0
//-----------------------------------
wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
wire replay0_mem_clk;
wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
@@ -1178,11 +1217,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #(
.THIS_PORTID (8),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.MEM_ADDR_W (30),
.MEM_DATA_W (64),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x300/x300_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-29T22:54:32.623216
// Source: x300_rfnoc_image_core.yml
// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
//
`define CHDR_WIDTH 64
top/x300/x310_rfnoc_image_core.v
+243 -204
View File
@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-29T22:54:33.009325
// Source: x310_rfnoc_image_core.yml
// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
//
`default_nettype none
module rfnoc_image_core #(
parameter CHDR_W = 64,
parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] PCIE_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
@@ -127,35 +129,50 @@ module rfnoc_image_core #(
// Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast,
input wire s_eth0_tvalid,
output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata,
output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast,
output wire m_eth0_tvalid,
input wire m_eth0_tready,
// Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata,
input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast,
input wire s_eth1_tvalid,
output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata,
output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast,
output wire m_eth1_tvalid,
input wire m_eth1_tready,
// Transport 2 (pcie)
input wire [CHDR_W-1:0] s_pcie_tdata,
input wire [PORT_W-1:0] s_pcie_tdata,
input wire s_pcie_tlast,
input wire s_pcie_tvalid,
output wire s_pcie_tready,
output wire [CHDR_W-1:0] m_pcie_tdata,
output wire [PORT_W-1:0] m_pcie_tdata,
output wire m_pcie_tlast,
output wire m_pcie_tvalid,
input wire m_pcie_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP2_W = 64;
localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8);
localparam EP3_W = 64;
localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -165,67 +182,77 @@ module rfnoc_image_core #(
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep2_tdata ;
wire [PORT_W-1:0] xb_to_ep2_tdata ;
wire xb_to_ep2_tlast ;
wire xb_to_ep2_tvalid;
wire xb_to_ep2_tready;
wire [CHDR_W-1:0] ep2_to_xb_tdata ;
wire [PORT_W-1:0] ep2_to_xb_tdata ;
wire ep2_to_xb_tlast ;
wire ep2_to_xb_tvalid;
wire ep2_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep3_tdata ;
wire [PORT_W-1:0] xb_to_ep3_tdata ;
wire xb_to_ep3_tlast ;
wire xb_to_ep3_tvalid;
wire xb_to_ep3_tready;
wire [CHDR_W-1:0] ep3_to_xb_tdata ;
wire [PORT_W-1:0] ep3_to_xb_tdata ;
wire ep3_to_xb_tlast ;
wire ep3_to_xb_tvalid;
wire ep3_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ;
wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ;
wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ;
wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ;
wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready;
chdr_crossbar_nxn #(
.CHDR_W (CHDR_W),
.PORT_W (PORT_W),
.NPORTS (9),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, PCIE_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0),
.MTU (MTU),
.ROUTES ({ 9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111111,
9'b111111100,
9'b111111010,
9'b111111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_xb_i (
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
@@ -252,26 +279,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 65536;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -279,7 +308,7 @@ module rfnoc_image_core #(
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -321,26 +350,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 0;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -348,7 +379,7 @@ module rfnoc_image_core #(
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -390,26 +421,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 65536;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready;
wire [CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid;
wire m_ep2_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata;
wire s_ep2_in0_tlast;
wire s_ep2_in0_tvalid;
wire s_ep2_in0_tready;
wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata;
wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast;
wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
wire m_ep2_ctrl_tready, s_ep2_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP2_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -417,7 +450,7 @@ module rfnoc_image_core #(
.INST_NUM (2),
.CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU),
.MTU (EP2_MTU),
.REPORT_STRM_ERRS (1)
) ep2_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -459,26 +492,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 0;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready;
wire [CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid;
wire m_ep3_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata;
wire s_ep3_in0_tlast;
wire s_ep3_in0_tvalid;
wire s_ep3_in0_tready;
wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata;
wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast;
wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
wire m_ep3_ctrl_tready, s_ep3_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP3_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -486,7 +521,7 @@ module rfnoc_image_core #(
.INST_NUM (3),
.CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU),
.MTU (EP3_MTU),
.REPORT_STRM_ERRS (1)
) ep3_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -528,26 +563,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -555,7 +592,7 @@ module rfnoc_image_core #(
.INST_NUM (4),
.CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU),
.MTU (EP4_MTU),
.REPORT_STRM_ERRS (1)
) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -597,26 +634,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -624,7 +663,7 @@ module rfnoc_image_core #(
.INST_NUM (5),
.CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU),
.MTU (EP5_MTU),
.REPORT_STRM_ERRS (1)
) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -773,23 +812,23 @@ module rfnoc_image_core #(
// duc0
//-----------------------------------
wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready;
wire [CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready;
wire duc0_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ;
wire s_duc0_in_0_tvalid;
wire s_duc0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_duc0_out_0_tdata ;
wire m_duc0_out_0_tlast ;
wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NUM_HB (3),
.CIC_MAX_INTERP (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_duc0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -818,23 +857,23 @@ module rfnoc_image_core #(
// ddc0
//-----------------------------------
wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
wire ddc0_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid;
wire s_ddc0_in_1_tready, s_ddc0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ;
wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ;
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NUM_HB (3),
.CIC_MAX_DECIM (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_ddc0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -863,15 +902,15 @@ module rfnoc_image_core #(
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -896,11 +935,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -946,23 +985,23 @@ module rfnoc_image_core #(
// duc1
//-----------------------------------
wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready;
wire [CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready;
wire duc1_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ;
wire s_duc1_in_0_tvalid;
wire s_duc1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_duc1_out_0_tdata ;
wire m_duc1_out_0_tlast ;
wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (5),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NUM_HB (3),
.CIC_MAX_INTERP (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_duc1_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -991,23 +1030,23 @@ module rfnoc_image_core #(
// ddc1
//-----------------------------------
wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
wire ddc1_ce_clk;
wire [BLOCK_CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid;
wire s_ddc1_in_1_tready, s_ddc1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ;
wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ;
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (6),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NUM_HB (3),
.CIC_MAX_DECIM (255),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_ddc1_4 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1036,15 +1075,15 @@ module rfnoc_image_core #(
// radio1
//-----------------------------------
wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
wire radio1_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid;
wire s_radio1_in_1_tready, s_radio1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ;
wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ;
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -1069,11 +1108,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -1119,15 +1158,15 @@ module rfnoc_image_core #(
// replay0
//-----------------------------------
wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
wire replay0_mem_clk;
wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
@@ -1178,11 +1217,11 @@ module rfnoc_image_core #(
rfnoc_block_replay #(
.THIS_PORTID (8),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (2),
.MEM_DATA_W (64),
.MEM_ADDR_W (30),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
top/x300/x310_rfnoc_image_core.vh
+1 -3
View File
@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,7 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-29T22:54:33.044163
// Source: x310_rfnoc_image_core.yml
// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
//
`define CHDR_WIDTH 64