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fpga: Update all RFNoC image core files

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Original-commit: 0fca5d5ffda1f5f4f7c966c3e5f5200222a5a575
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent fae19151c4
commit aeaf219f77
26 changed files with 2604 additions and 2161 deletions
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top/n3xx/n320_bist_image_core.v
+151 -122
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,16 +13,18 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-29T22:54:30.534235
// Source: n320_bist_image_core.yml
// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
//
`default_nettype none
module rfnoc_image_core #(
parameter CHDR_W = 64,
parameter [31:0] CHDR_W = 64,
parameter [31:0] PORT_W = 64,
parameter [31:0] ETH0_W = 64,
parameter [31:0] ETH1_W = 64,
parameter [31:0] DMA_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
@@ -126,35 +128,46 @@ module rfnoc_image_core #(
// Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire [PORT_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast,
input wire s_eth0_tvalid,
output wire s_eth0_tready,
output wire [CHDR_W-1:0] m_eth0_tdata,
output wire [PORT_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast,
output wire m_eth0_tvalid,
input wire m_eth0_tready,
// Transport 1 (eth1)
input wire [CHDR_W-1:0] s_eth1_tdata,
input wire [PORT_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast,
input wire s_eth1_tvalid,
output wire s_eth1_tready,
output wire [CHDR_W-1:0] m_eth1_tdata,
output wire [PORT_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast,
output wire m_eth1_tvalid,
input wire m_eth1_tready,
// Transport 2 (dma)
input wire [CHDR_W-1:0] s_dma_tdata,
input wire [PORT_W-1:0] s_dma_tdata,
input wire s_dma_tlast,
input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata,
output wire [PORT_W-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
localparam EP0_W = 64;
localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
localparam EP1_W = 64;
localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
localparam EP4_W = 64;
localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
localparam EP5_W = 64;
localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
@@ -164,51 +177,59 @@ module rfnoc_image_core #(
// CHDR Crossbar
//---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire [PORT_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ;
wire [PORT_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ;
wire [PORT_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ;
wire [PORT_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep4_tdata ;
wire [PORT_W-1:0] xb_to_ep4_tdata ;
wire xb_to_ep4_tlast ;
wire xb_to_ep4_tvalid;
wire xb_to_ep4_tready;
wire [CHDR_W-1:0] ep4_to_xb_tdata ;
wire [PORT_W-1:0] ep4_to_xb_tdata ;
wire ep4_to_xb_tlast ;
wire ep4_to_xb_tvalid;
wire ep4_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep5_tdata ;
wire [PORT_W-1:0] xb_to_ep5_tdata ;
wire xb_to_ep5_tlast ;
wire xb_to_ep5_tvalid;
wire xb_to_ep5_tready;
wire [CHDR_W-1:0] ep5_to_xb_tdata ;
wire [PORT_W-1:0] ep5_to_xb_tdata ;
wire ep5_to_xb_tlast ;
wire ep5_to_xb_tvalid;
wire ep5_to_xb_tready;
chdr_crossbar_nxn #(
.CHDR_W (CHDR_W),
.PORT_W (PORT_W),
.NPORTS (7),
.CHDR_WIDTHS ({EP5_W, EP4_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
.DEFAULT_PORT (0),
.MTU (MTU),
.ROUTES ({ 7'b1111111,
7'b1111111,
7'b1111111,
7'b1111111,
7'b1111100,
7'b1111010,
7'b1111001 }),
.BYTE_MTU (BYTE_MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (3),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_xb_i (
) chdr_crossbar_nxn_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
@@ -235,26 +256,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP0_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -262,7 +285,7 @@ module rfnoc_image_core #(
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU),
.MTU (EP0_MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -304,26 +327,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP1_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -331,7 +356,7 @@ module rfnoc_image_core #(
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU),
.MTU (EP1_MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -373,26 +398,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 32768;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid;
wire m_ep4_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
wire s_ep4_in0_tlast;
wire s_ep4_in0_tvalid;
wire s_ep4_in0_tready;
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP4_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -400,7 +427,7 @@ module rfnoc_image_core #(
.INST_NUM (2),
.CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU),
.MTU (EP4_MTU),
.REPORT_STRM_ERRS (1)
) ep4_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -442,26 +469,28 @@ module rfnoc_image_core #(
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 32768;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid;
wire m_ep5_out0_tready;
wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
wire s_ep5_in0_tlast;
wire s_ep5_in0_tvalid;
wire s_ep5_in0_tready;
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
chdr_stream_endpoint #(
.DEVICE_FAMILY ("7SERIES"),
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.CHDR_W (EP5_W),
.BLOCK_CHDR_W (BLOCK_CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
@@ -469,7 +498,7 @@ module rfnoc_image_core #(
.INST_NUM (3),
.CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU),
.MTU (EP5_MTU),
.REPORT_STRM_ERRS (1)
) ep5_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -602,15 +631,15 @@ module rfnoc_image_core #(
// radio0
//-----------------------------------
wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ;
wire s_radio0_in_0_tvalid;
wire s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_0_tdata ;
wire m_radio0_out_0_tlast ;
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
wire radio0_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ;
wire s_radio0_in_0_tvalid;
wire s_radio0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ;
wire m_radio0_out_0_tlast ;
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
@@ -635,11 +664,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -685,15 +714,15 @@ module rfnoc_image_core #(
// radio1
//-----------------------------------
wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ;
wire s_radio1_in_0_tvalid;
wire s_radio1_in_0_tready;
wire [CHDR_W-1:0] m_radio1_out_0_tdata ;
wire m_radio1_out_0_tlast ;
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
wire radio1_radio_clk;
wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ;
wire s_radio1_in_0_tvalid;
wire s_radio1_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ;
wire m_radio1_out_0_tlast ;
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
@@ -718,11 +747,11 @@ module rfnoc_image_core #(
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (1),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
@@ -768,15 +797,15 @@ module rfnoc_image_core #(
// fifo0
//-----------------------------------
wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
wire fifo0_mem_clk;
wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
@@ -827,7 +856,7 @@ module rfnoc_image_core #(
rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.CHDR_W (BLOCK_CHDR_W),
.NUM_PORTS (4),
.MEM_DATA_W (64),
.MEM_ADDR_W (31),
@@ -836,7 +865,7 @@ module rfnoc_image_core #(
.MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (),
.MTU (MTU)
.MTU (BLOCK_MTU)
) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),