miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: sim: Allow DATA_WIDTH that's not a multiple of 8

Browse Source 
Original-commit: f1173f14d18feb5fb40285b393d0d5bc286acd17
This commit is contained in:
Wade Fife
2025-02-12 22:06:20 -06:00
parent 30180c36f0
commit ac04bb81c4
1 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sim/rfnoc/PkgAxiStreamBfm.sv
+7 -2
View File
@@ -85,8 +85,11 @@ package PkgAxiStreamBfm;
// Type Definitions
//------------------
// Round up width of TKEEP when TDATA is not a multiple of 8
localparam int KEEP_WIDTH = (DATA_WIDTH+7)/8;
typedef logic [DATA_WIDTH-1:0] data_t; // Single bus TDATA word
typedef logic [DATA_WIDTH/8-1:0] keep_t; // Single TKEEP word
typedef logic [KEEP_WIDTH-1:0] keep_t; // Single TKEEP word
typedef logic [USER_WIDTH-1:0] user_t; // Single TUSER word
typedef AxiStreamPacket #(DATA_WIDTH, USER_WIDTH) AxisPacket_t;
@@ -285,13 +288,15 @@ package PkgAxiStreamBfm;
// Properties
//------------
localparam int KEEP_WIDTH = AxisPacket_t::KEEP_WIDTH;
// Default stall probability, as a percentage (0-100).
local const int DEF_STALL_PROB = 38;
// Default values to use for idle bus cycles
local const AxisPacket_t::data_t IDLE_DATA = {DATA_WIDTH{1'bX}};
local const AxisPacket_t::user_t IDLE_USER = {(USER_WIDTH > 1 ? USER_WIDTH : 1){1'bX}};
local const AxisPacket_t::keep_t IDLE_KEEP = {(DATA_WIDTH/8){1'bX}};
local const AxisPacket_t::keep_t IDLE_KEEP = {KEEP_WIDTH{1'bX}};
// Virtual interfaces for master and slave connections to DUT
local virtual AxiStreamIf #(DATA_WIDTH,USER_WIDTH,MAX_PACKET_BYTES,