fpga: lib: Add clock domain comments to interfaces

Original-commit: c64258e09b221d0bfeb55e01085a20e37c5b62ba

lib/rfnoc/xport_sv/eth_ipv4_interface.sv

@@ -19,7 +19,8 @@
 //   - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
 //   - PREAMBLE_BYTES: Number of bytes of Preamble expected
 //   - ADD_SOF: Add a SOF indication into the tuser field of e2c
-//   - SYNC: Set if MAC is not the same as bus_clk
+//   - SYNC: Set if the CPU clock domain (c2e, e2c) is not the same as the
+//           Ethernet clock domain (eth_rx, eth_tx).
 //   - ENET_W: Width of the link to the Ethernet MAC
 //   - CPU_W: Width of the CPU interface
 //   - CHDR_W: Width of the CHDR interface
@@ -63,15 +64,19 @@ module eth_ipv4_interface #(
   output logic [31:0] my_ip,
   output logic [15:0] my_udp_chdr_port,
 
-  // Ethernet MAC
+  // Ethernet MAC (domain: eth_rx.clk)
   output logic       eth_pause_req,
   AxiStreamIf.master eth_tx, // tUser = {1'b0,trailing bytes};
   AxiStreamIf.slave  eth_rx, // tUser = {error,trailing bytes};
-  // CHDR router interface
+
+  // CHDR router interface (domain: eth_rx.clk)
   AxiStreamIf.master e2v, // tUser = {*not used*};
   AxiStreamIf.slave  v2e, // tUser = {*not used*};
+
   // CPU DMA
+  // (domain: e2c.clk if SYNC=0, else eth_rx.clk)
   AxiStreamIf.master e2c, // tUser = {sof,trailing bytes};
+  // (domain: c2e.clk if SYNC=0, else eth_rx.clk)
   AxiStreamIf.slave  c2e  // tUser = {1'b0,trailing bytes};
 
  );