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fpga: lib: Add clock domain comments to interfaces

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Original-commit: c64258e09b221d0bfeb55e01085a20e37c5b62ba
This commit is contained in:
Wade Fife
2021-06-03 11:26:54 -05:00
committed by Aaron Rossetto
parent b7bd308e9c
commit ab09eb9b09
7 changed files with 28 additions and 13 deletions
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lib/axi4_sv/axi.vh
+3 -2
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@@ -3,8 +3,9 @@
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header File: AxiIf.vh
// Description: Macros for use with AXI4(FULL)
// Header File: axi.vh
//
// Description: Macros for use with AxiIf (AXI4 full)
//
//-----------------------------------------------------------------------------