diff --git a/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci b/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci
index aa790b7..905482a 100644
--- a/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci
+++ b/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci
@@ -3,7 +3,7 @@
   "ip_inst": {
     "xci_name": "b200_clk_gen",
     "component_reference": "xilinx.com:ip:clk_wiz:6.0",
-    "ip_revision": "14",
+    "ip_revision": "19",
     "gen_directory": "../../../../B210_Project_Firmwire.gen/sources_1/ip/b200_clk_gen",
     "parameters": {
       "component_parameters": {
@@ -583,27 +583,27 @@
         "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "kintex7" } ],
-        "BASE_BOARD_PART": [ { "value": "" } ],
-        "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7k325t" } ],
-        "NEXTGEN_VERSAL": [ { "value": "0" } ],
-        "PACKAGE": [ { "value": "ffg676" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
-        "SILICON_REVISION": [ { "value": "" } ],
-        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
-        "SPEEDGRADE": [ { "value": "-2" } ],
-        "STATIC_POWER": [ { "value": "" } ],
-        "TEMPERATURE_GRADE": [ { "value": "" } ]
+        "ARCHITECTURE": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "BASE_BOARD_PART": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "BOARD_CONNECTIONS": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "DEVICE": [ { "value": "xc7k325t", "resolve_type": "generated", "usage": "all" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "PACKAGE": [ { "value": "ffg676", "resolve_type": "generated", "usage": "all" } ],
+        "PREFHDL": [ { "value": "VERILOG", "resolve_type": "generated", "usage": "all" } ],
+        "SILICON_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED", "resolve_type": "generated", "usage": "all" } ],
+        "SPEEDGRADE": [ { "value": "-2", "resolve_type": "generated", "usage": "all" } ],
+        "STATIC_POWER": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "TEMPERATURE_GRADE": [ { "value": "", "resolve_type": "generated", "usage": "all" } ]
       },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
-        "IPREVISION": [ { "value": "14" } ],
+        "IPREVISION": [ { "value": "19" } ],
         "MANAGED": [ { "value": "TRUE" } ],
         "OUTPUTDIR": [ { "value": "../../../../B210_Project_Firmwire.gen/sources_1/ip/b200_clk_gen" } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
-        "SWVERSION": [ { "value": "2024.1" } ],
+        "SWVERSION": [ { "value": "2026.1" } ],
         "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
       }
     },
@@ -701,5 +701,6 @@
         }
       }
     }
-  }
+  },
+  "checksum": "c9a09a6a"
 }
\ No newline at end of file
diff --git a/vivado/b210_k7/project_config.tcl b/vivado/b210_k7/project_config.tcl
index df0bf47..df85b34 100644
--- a/vivado/b210_k7/project_config.tcl
+++ b/vivado/b210_k7/project_config.tcl
@@ -7,7 +7,7 @@ set B210_TOP          "b200"
 set B210_PART         "xc7k325tffg676-2"
 
 # Historical baseline. Change this to 2026.1 in the Vivado migration commit.
-set B210_EXPECTED_VIVADO "2024.1"
+set B210_EXPECTED_VIVADO "2026.1"
 
 # Default parallelism. Override with environment variable B210_JOBS.
 set B210_DEFAULT_JOBS 8