fpga: x400: zbx: Add support for XO3 CPLD variant.

The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
  to include XO3 PLL
- Add ability to shift outgoing data for
  the GPIO communication interface with
  the X410 FPGA.
- Include project files required to build
  the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.


Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b

top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v

@@ -370,10 +370,16 @@ module switch_control #(
     rx1_switch_11_reg  <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];
   end
 
+`ifdef VARIANT_XO3
+  localparam RAM_RW_MODE = "B-READ-ONLY" ;
+`else
+  localparam RAM_RW_MODE = "READ-FIRST" ;
+`endif
+
   ram_2port #(
     .DWIDTH     (32),
     .AWIDTH     (8),
-    .RW_MODE    ("READ-FIRST"),
+    .RW_MODE    (RAM_RW_MODE),
     .RAM_TYPE   ("AUTOMATIC"),
     .OUT_REG    (0),
     .INIT_FILE  ("register_endpoints/memory_init_files/tx0_path_defaults.hex")
@@ -394,7 +400,7 @@ module switch_control #(
   ram_2port #(
     .DWIDTH     (32),
     .AWIDTH     (8),
-    .RW_MODE    ("READ-FIRST"),
+    .RW_MODE    (RAM_RW_MODE),
     .RAM_TYPE   ("AUTOMATIC"),
     .OUT_REG    (0),
     .INIT_FILE  ("register_endpoints/memory_init_files/tx1_path_defaults.hex")
@@ -415,7 +421,7 @@ module switch_control #(
   ram_2port #(
     .DWIDTH     (32),
     .AWIDTH     (8),
-    .RW_MODE    ("READ-FIRST"),
+    .RW_MODE    (RAM_RW_MODE),
     .RAM_TYPE   ("AUTOMATIC"),
     .OUT_REG    (0),
     .INIT_FILE  ("register_endpoints/memory_init_files/rx0_path_defaults.hex")
@@ -436,7 +442,7 @@ module switch_control #(
   ram_2port #(
     .DWIDTH     (32),
     .AWIDTH     (8),
-    .RW_MODE    ("READ-FIRST"),
+    .RW_MODE    (RAM_RW_MODE),
     .RAM_TYPE   ("AUTOMATIC"),
     .OUT_REG    (0),
     .INIT_FILE  ("register_endpoints/memory_init_files/rx1_path_defaults.hex")