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fpga: x400: zbx: Add support for XO3 CPLD variant.

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The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
  to include XO3 PLL
- Add ability to shift outgoing data for
  the GPIO communication interface with
  the X410 FPGA.
- Include project files required to build
  the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.


Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This commit is contained in:
Javier Valenzuela
2022-06-28 16:33:05 -05:00
committed by Wade Fife
parent 27aae37722
commit a6fc53b4e6
23 changed files with 1888 additions and 84 deletions
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top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v
+14 -8
View File
@@ -369,10 +369,16 @@ module dsa_control #(
wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain;
wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain;
`ifdef VARIANT_XO3
localparam RAM_RW_MODE = "B-READ-ONLY" ;
`else
localparam RAM_RW_MODE = "READ-FIRST" ;
`endif
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
@@ -394,7 +400,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
@@ -416,7 +422,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
@@ -438,7 +444,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
@@ -464,7 +470,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
@@ -486,7 +492,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
@@ -508,7 +514,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
@@ -530,7 +536,7 @@ module dsa_control #(
ram_2port #(
.DWIDTH (32),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RW_MODE (RAM_RW_MODE),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0),
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")