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fpga: x400: zbx: Add support for XO3 CPLD variant.

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The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
  to include XO3 PLL
- Add ability to shift outgoing data for
  the GPIO communication interface with
  the X410 FPGA.
- Include project files required to build
  the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.


Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This commit is contained in:
Javier Valenzuela
2022-06-28 16:33:05 -05:00
committed by Wade Fife
parent 27aae37722
commit a6fc53b4e6
23 changed files with 1888 additions and 84 deletions
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top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx
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<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="pll" module="pll" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2022 03 03 14:15:50.923" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
<Package>
<File name="pll.lpc" type="lpc" modified="2022 03 03 14:15:48.492"/>
<File name="pll.v" type="top_level_verilog" modified="2022 03 03 14:15:48.597"/>
<File name="pll_tmpl.v" type="template_verilog" modified="2022 03 03 14:15:48.597"/>
</Package>
</DiamondModule>