fpga: x400: zbx: Add support for XO3 CPLD variant.
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This commit is contained in:
Javier Valenzuela
committed by
Wade Fife
Wade Fife
parent
27aae37722
commit
a6fc53b4e6
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<?xml version="1.0" encoding="UTF-8"?>
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<DiamondModule name="pll" module="pll" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2022 03 03 14:15:50.923" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
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<Package>
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<File name="pll.lpc" type="lpc" modified="2022 03 03 14:15:48.492"/>
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<File name="pll.v" type="top_level_verilog" modified="2022 03 03 14:15:48.597"/>
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<File name="pll_tmpl.v" type="template_verilog" modified="2022 03 03 14:15:48.597"/>
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</Package>
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</DiamondModule>
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[Device]
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Family=machxo3lf
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PartType=LCMXO3LF-9400C
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PartName=LCMXO3LF-9400C-6BG256I
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SpeedGrade=6
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Package=CABGA256
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OperatingCondition=IND
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Status=S
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[IP]
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VendorName=Lattice Semiconductor Corporation
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CoreType=LPM
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CoreStatus=Demo
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CoreName=PLL
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CoreRevision=5.8
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ModuleName=pll
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SourceFormat=Verilog HDL
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ParameterFileVersion=1.0
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Date=03/03/2022
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Time=14:15:48
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[Parameters]
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Verilog=1
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VHDL=0
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EDIF=1
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Destination=Synplicity
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Expression=None
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Order=None
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IO=0
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mode=Frequency
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CLKI=64
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CLKI_DIV=1
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BW=6.139
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VCO=512.000
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fb_mode=CLKOP
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CLKFB_DIV=1
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FRACN_ENABLE=0
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FRACN_DIV=0
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DynamicPhase=STATIC
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ClkEnable=1
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Standby=0
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Enable_sel=0
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PLLRst=0
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PLLMRst=0
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ClkOS2Rst=0
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ClkOS3Rst=0
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LockSig=1
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LockStk=0
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WBProt=0
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OPBypass=0
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OPUseDiv=0
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CLKOP_DIV=8
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FREQ_PIN_CLKOP=64
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OP_Tol=0.0
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CLKOP_AFREQ=64.000000
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CLKOP_PHASEADJ=0
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CLKOP_TRIM_POL=Rising
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CLKOP_TRIM_DELAY=0
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EnCLKOS=1
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OSBypass=0
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OSUseDiv=0
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CLKOS_DIV=8
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FREQ_PIN_CLKOS=64
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OS_Tol=0.0
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CLKOS_AFREQ=64.000000
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CLKOS_PHASEADJ=225
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CLKOS_TRIM_POL=Rising
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CLKOS_TRIM_DELAY=0
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EnCLKOS2=0
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OS2Bypass=0
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OS2UseDiv=0
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CLKOS2_DIV=1
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FREQ_PIN_CLKOS2=64
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OS2_Tol=0.0
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CLKOS2_AFREQ=64.000000
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CLKOS2_PHASEADJ=225
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EnCLKOS3=0
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OS3Bypass=0
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OS3UseDiv=0
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CLKOS3_DIV=1
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FREQ_PIN_CLKOS3=100
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OS3_Tol=0.0
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CLKOS3_AFREQ=
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CLKOS3_PHASEADJ=0
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[Command]
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cmd_line= -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock
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@@ -0,0 +1,100 @@
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/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
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/* Module Version: 5.7 */
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/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock */
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/* Thu Mar 03 14:15:48 2022 */
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`timescale 1 ns / 1 ps
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module pll (CLKI, ENCLKOP, ENCLKOS, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK=1 */;
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input wire CLKI;
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input wire ENCLKOP;
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input wire ENCLKOS;
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output wire CLKOP;
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output wire CLKOS;
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output wire LOCK;
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wire CLKOS_t;
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wire CLKOP_t;
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wire scuba_vlo;
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VLO scuba_vlo_inst (.Z(scuba_vlo));
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defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
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defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
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defparam PLLInst_0.MRST_ENA = "DISABLED" ;
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defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
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defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
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defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
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defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
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defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
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defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
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defparam PLLInst_0.CLKOS_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS_CPHASE = 12 ;
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defparam PLLInst_0.CLKOP_FPHASE = 0 ;
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defparam PLLInst_0.CLKOP_CPHASE = 7 ;
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defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
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defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
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defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
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defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
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defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
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defparam PLLInst_0.FRACN_DIV = 0 ;
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defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
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defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
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defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
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defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
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defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
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defparam PLLInst_0.CLKOP_ENABLE = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_DIV = 1 ;
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defparam PLLInst_0.CLKOS2_DIV = 1 ;
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defparam PLLInst_0.CLKOS_DIV = 8 ;
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defparam PLLInst_0.CLKOP_DIV = 8 ;
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defparam PLLInst_0.CLKFB_DIV = 1 ;
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defparam PLLInst_0.CLKI_DIV = 1 ;
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defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
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EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
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.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
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.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
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.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
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.ENCLKOP(ENCLKOP), .ENCLKOS(ENCLKOS), .ENCLKOS2(scuba_vlo), .ENCLKOS3(scuba_vlo),
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.PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo), .PLLWE(scuba_vlo),
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.PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
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.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
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.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
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.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
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.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(),
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.CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
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.PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
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.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
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/* synthesis FREQUENCY_PIN_CLKOS="64.000000" */
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/* synthesis FREQUENCY_PIN_CLKOP="64.000000" */
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/* synthesis FREQUENCY_PIN_CLKI="64.000000" */
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/* synthesis ICP_CURRENT="9" */
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/* synthesis LPF_RESISTOR="72" */;
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assign CLKOS = CLKOS_t;
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assign CLKOP = CLKOP_t;
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// exemplar begin
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 64.000000
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 64.000000
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 64.000000
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// exemplar attribute PLLInst_0 ICP_CURRENT 9
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// exemplar attribute PLLInst_0 LPF_RESISTOR 72
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// exemplar end
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endmodule
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@@ -0,0 +1,7 @@
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/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
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/* Module Version: 5.7 */
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/* Thu Mar 03 14:15:48 2022 */
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/* parameterized module instance */
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pll __ (.CLKI( ), .ENCLKOP( ), .ENCLKOS( ), .CLKOP( ), .CLKOS( ),
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.LOCK( ));
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