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fpga: n3xx: Fix clock frequency comments

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Original-commit: 40f0d8e4e59a4d13a6d9b7ac07b4d649a5c813f9
This commit is contained in:
Wade Fife
2022-03-26 21:52:26 -05:00
parent 1dd8058c08
commit a0987ea0f8
1 changed files with 2 additions and 2 deletions
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top/n3xx/n3xx_clocking.v
+2 -2
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@@ -129,8 +129,8 @@ module n3xx_clocking (
// Output Output Phase Duty Cycle Pk-to-Pk Phase // Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// CLK_OUT1___170.543______0.000______50.0______105.052_____94.905 (meas_clk) // meas_clk___198.413______0.000______50.0______113.755____141.292
// CLK_OUT2___305.556______0.000______50.0_______93.867_____94.905 (ddr3_dma_clk) // ddr3_dma_clk___303.819______0.000______50.0______105.705____141.292
// //
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI) // Input Clock Freq (MHz) Input Jitter (UI)