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fpga: n3xx: rh: cpld: Refactor CPLD build process

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Original-commit: 739b37ba40e7aba288ed781922aa8fa3b1bfc16e
This commit is contained in:
Humberto Jimenez
2022-01-25 18:28:57 -07:00
committed by Wade Fife
parent f645d3d613
commit 95c58d5ed6
6 changed files with 122 additions and 27 deletions
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top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
# Date created = 08:22:34 September 13, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "08:22:34 September 13, 2017"
# Revisions
PROJECT_REVISION = "rhodium_top"