fpga: n3xx: rh: cpld: Refactor CPLD build process
Original-commit: 739b37ba40e7aba288ed781922aa8fa3b1bfc16e
This commit is contained in:
Humberto Jimenez
committed by
Wade Fife
Wade Fife
parent
f645d3d613
commit
95c58d5ed6
@@ -0,0 +1,7 @@
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# Ignore Quartus generated files upon project opening.
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*.qws
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db/
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incremental_db/
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output_files/
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*.sopcinfo
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build/
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@@ -1,27 +1,78 @@
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#
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# Copyright 2018 Ettus Research, a National Instruments Company
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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.PHONY: all clean
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP N32x CPLD Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/usrp_n320_rh_cpld.pof: Bitstream to use with JTAG programmer
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## build/usrp_n320_rh_cpld.svf: Bitstream to use with PS JTAG engine
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# Definitions
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10M04_ID = "10M04SAU169I7G"
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TARGET = bin
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TOP ?= rhodium_top
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# quartus_build($1=Device, $2=Definitions)
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quartus_build = make -f Makefile.cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Artifact Name)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p build/; \
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echo "Exporting bitstream files..."; \
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cp build-$@/output_files/$(TOP).pof build/$(1).pof; \
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cp build-$@/output_files/$(TOP).svf build/$(1).svf; \
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echo -ne "\n\n---- Make: CPLD ready!\n"; \
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echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \
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echo -ne " build/$(1).svf via PS JTAG-engine\n";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Supported Targets
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##-----------------
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all: N320_CPLD_10M04 ##(Default target)
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##N320_CPLD_10M04: N320/1 CPLD targeted to 10M04SAU169I7G.
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N320_CPLD_10M04:
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$(call quartus_build,$(10M04_ID),$(DEFS))
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$(call post_build,"usrp_n320_rh_cpld")
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clean: ##Clean up all target build outputs.
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@echo -ne "\nCleaning targets and git repo...\n";
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@rm -rf build-N320_CPLD*
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@rm -rf build
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@git clean -Xdf
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cleanall: ##Clean up all target and ip build outputs.
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@echo -ne "\nCleaning targets, IP, and git repo...\n";
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@rm -rf build-N320_CPLD*
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@rm -rf build
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@rm -rf build-ip
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@git clean -Xdf
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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SRCS=rhodium_top.qpf rhodium_top.qsf rhodium_top.sdc rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
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SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
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SHORT_HASH=$(addprefix GIT_HASH=,$(shell ../../../../../tools/scripts/git-hash.sh))
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all: cpld-rhodium-revb.svf
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output_files/rhodium_top.pof: $(SRCS)
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quartus_map rhodium_top --verilog_macro="$(SHORT_HASH)"
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quartus_fit rhodium_top
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quartus_asm rhodium_top
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quartus_sta rhodium_top
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cpld-rhodium-revb.svf: output_files/rhodium_top.pof
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quartus_cpf --convert --frequency 10.0MHz --voltage 2.5 --operation p $? $@
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clean:
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rm -rf db incremental_db output_files simulation cpld-rhodium-revb.svf
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a.out: $(SIM_SRCS)
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iverilog -tvvp -D$(SHORT_HASH) -s rh_tb $(SIM_SRCS)
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##
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##Supported Options
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##-----------------
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##
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@@ -0,0 +1,36 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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PROJECT_DIR = $(abspath .)
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BASE_DIR = $(abspath ../../../..)
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include $(BASE_DIR)/../tools/make/quartus_design_builder.mak
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# Define VERILOG_DEFS for macros definition
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VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF)
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bin: .prereqs
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$(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),,0)
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@\
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pushd $(BUILD_DIR); \
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echo "Converting bitfile to svf format..."; \
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quartus_cpf --convert \
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--frequency 10.0MHz \
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--voltage 2.5 \
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--operation p \
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output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE).svf; \
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popd;
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+8
-7
@@ -286,14 +286,15 @@ set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
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set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
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set_global_assignment -name VERILOG_FILE rhodium_top.v
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set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v
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set_global_assignment -name VERILOG_FILE rhodium_gain_table.v
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set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v
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set_global_assignment -name VERILOG_FILE rh_tb.v
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set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb
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set_global_assignment -name VERILOG_FILE ../rhodium_top.v
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set_global_assignment -name VERILOG_FILE ../rhodium_gain_ctrl.v
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set_global_assignment -name VERILOG_FILE ../rhodium_gain_table.v
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set_global_assignment -name VERILOG_FILE ../rhodium_lo_gain.v
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set_global_assignment -name VERILOG_FILE ../rh_tb.v
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set_global_assignment -name EDA_TEST_BENCH_FILE ../rh_tb.v -section_id rh_tb
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set_global_assignment -name SDC_FILE ../rhodium_top.sdc
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set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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@@ -128,9 +128,9 @@ output Cal_iso_Sw_Ctrl
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/* PS SPI */
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localparam GIT_HASH = 36'h`GIT_HASH;
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localparam GIT_HASH = `GIT_HASH;
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localparam PROD_SIGNATURE = 16'h0045; // Product signature (Rhodium atomic number in BCD)
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localparam REVISION_MINOR = 16'h0002;
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localparam REVISION_MINOR = 16'h0003;
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localparam REVISION_MAJOR = 16'h0004;
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localparam CPLD_BUILD_LSB = GIT_HASH[15:0]; // Build code LSB
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localparam CPLD_BUILD_MSB = GIT_HASH[31:16]; // Build code MSB
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