fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters
Original-commit: 8444f84add04f025b7e24855e0ba79446e615e01
This commit is contained in:
committed by
Wade Fife
parent
01f7f75ca3
commit
83ad8e36ba
@@ -13,11 +13,11 @@
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// that are always set to zero, and using internal DSP slice registers to
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// hold coefficients.
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//
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// For the most efficient DSP slice inference use these settings, set
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// For the most efficient DSP slice inference use these settings, set
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// COEFF_WIDTH to be less than 18.
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//
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// Parameters:
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//
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//
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// COEFF_WIDTH : Coefficient width
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//
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// NUM_COEFFS : Number of coefficients / filter taps
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@@ -29,6 +29,9 @@
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// RELOADABLE_COEFFS : Enable (1) or disable (0) reloading
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// coefficients at runtime
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//
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// BLANK_OUTPUT : Disable (1) or enable (0) output when initially
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// filling internal pipeline
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//
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// SYMMETRIC_COEFFS : Reduce multiplier usage by approximately half
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// if coefficients are symmetric
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//
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@@ -41,7 +44,7 @@
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// streaming will cause temporary output
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// corruption!
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//
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// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
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// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
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// least once since COEFFS_VEC is ignored!
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//
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@@ -56,11 +59,12 @@ module rfnoc_block_fir_filter #(
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parameter COEFF_WIDTH = 16,
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parameter NUM_COEFFS = 41,
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parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = // Make impulse by default
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{
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{
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{1'b0, {(COEFF_WIDTH-1){1'b1}} }, // Max positive value
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{(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}} // Zero for remaining coefficients
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},
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parameter RELOADABLE_COEFFS = 1,
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parameter BLANK_OUTPUT = 1,
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parameter SYMMETRIC_COEFFS = 0,
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parameter SKIP_ZERO_COEFFS = 0,
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parameter USE_EMBEDDED_REGS_COEFFS = 1
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@@ -161,7 +165,7 @@ module rfnoc_block_fir_filter #(
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) noc_shell_fir_filter_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.ce_clk (ce_clk),
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.ce_clk (ce_clk),
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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.ce_rst (ce_rst),
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@@ -280,6 +284,7 @@ module rfnoc_block_fir_filter #(
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.NUM_COEFFS (NUM_COEFFS),
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.COEFFS_VEC (COEFFS_VEC),
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.RELOADABLE_COEFFS (RELOADABLE_COEFFS),
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.BLANK_OUTPUT (BLANK_OUTPUT),
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.SYMMETRIC_COEFFS (SYMMETRIC_COEFFS),
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.SKIP_ZERO_COEFFS (SKIP_ZERO_COEFFS),
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.USE_EMBEDDED_REGS_COEFFS (USE_EMBEDDED_REGS_COEFFS)
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@@ -17,7 +17,7 @@
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//
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// BASE_ADDR : Control port base address to which this block
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// responds.
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//
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//
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// COEFF_WIDTH : Coefficient width
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//
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// NUM_COEFFS : Number of coefficients / filter taps
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@@ -29,6 +29,9 @@
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// RELOADABLE_COEFFS : Enable (1) or disable (0) reloading
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// coefficients at runtime
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//
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// BLANK_OUTPUT : Disable (1) or enable (0) output when initially
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// filling internal pipeline
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//
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// SYMMETRIC_COEFFS : Reduce multiplier usage by approximately half
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// if coefficients are symmetric
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//
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@@ -41,7 +44,7 @@
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// streaming will cause temporary output
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// corruption!
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//
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// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
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// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
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// least once since COEFFS_VEC is ignored!
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@@ -53,11 +56,12 @@ module rfnoc_fir_filter_core #(
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parameter COEFF_WIDTH = 16,
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parameter NUM_COEFFS = 41,
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parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = // Make impulse by default
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{
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{
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{1'b0, {(COEFF_WIDTH-1){1'b1}} }, // Max positive value
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{(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}} // Zero for remaining coefficients
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},
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parameter RELOADABLE_COEFFS = 1,
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parameter BLANK_OUTPUT = 1,
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parameter SYMMETRIC_COEFFS = 0,
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parameter SKIP_ZERO_COEFFS = 0,
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parameter USE_EMBEDDED_REGS_COEFFS = 1
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@@ -171,7 +175,7 @@ module rfnoc_fir_filter_core #(
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.NUM_COEFFS (NUM_COEFFS),
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.COEFFS_VEC (COEFFS_VEC),
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.RELOADABLE_COEFFS (RELOADABLE_COEFFS),
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.BLANK_OUTPUT (1),
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.BLANK_OUTPUT (BLANK_OUTPUT),
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// Optional optimizations
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.SYMMETRIC_COEFFS (SYMMETRIC_COEFFS),
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.SKIP_ZERO_COEFFS (SKIP_ZERO_COEFFS),
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@@ -202,7 +206,7 @@ module rfnoc_fir_filter_core #(
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.NUM_COEFFS (NUM_COEFFS),
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.COEFFS_VEC (COEFFS_VEC),
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.RELOADABLE_COEFFS (RELOADABLE_COEFFS),
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.BLANK_OUTPUT (1),
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.BLANK_OUTPUT (BLANK_OUTPUT),
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// Optional optimizations
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.SYMMETRIC_COEFFS (SYMMETRIC_COEFFS),
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.SKIP_ZERO_COEFFS (SKIP_ZERO_COEFFS),
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