miegl/b210-k7-fpga
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fpga: Add option to specify build output directory

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Original-commit: 58fb72a82da8bb638dbdfe44d3be84e8382c10a2
This commit is contained in:
Wade Fife
2024-03-15 20:08:15 -05:00
parent 600df8752c
commit 822d1bd26d
7 changed files with 138 additions and 127 deletions
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tools/make/viv_design_builder.mak
+1 -1
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@@ -30,7 +30,7 @@ BUILD_VIVADO_DESIGN = \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
export VIV_INCR_BUILD=$(INCR_BUILD); \
cd $(BUILD_DIR); \
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(MAKEFILE_DIR)/dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
# -------------------------------------------------------------------
tools/make/viv_preamble.mak
+4 -2
View File
@@ -27,7 +27,10 @@ SIMLIB_DIR = $(abspath $(BASE_DIR)/../sim)
LIB_IP_DIR = $(abspath $(LIB_DIR)/ip)
HLS_IP_DIR = $(abspath $(LIB_DIR)/hls)
BUILD_BASE_DIR ?= .
MAKEFILE_DIR = $(abspath .)
IP_BUILD_DIR ?= $(abspath ./build-ip/$(subst /,,$(PART_ID)))
BUILD_BASE_DIR ?= $(abspath .)
ifdef NAME
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
@@ -35,7 +38,6 @@ else
BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
endif
IP_BUILD_DIR = $(abspath ./build-ip/$(subst /,,$(PART_ID)))
# -------------------------------------------------------------------
# Git Hash Retrieval