fpga: rfnoc: Add new FFT block
This replaces the legacy RFNoC FFT block with a new one of the same name that includes a superset of the original features. New features include cyclic prefix insertion or removal and FFT sizes up to 64k. Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
This commit is contained in:
Wade Fife
committed by
Jörg Hofrichter
Jörg Hofrichter
parent
0770fd4405
commit
81f150213f
@@ -0,0 +1,623 @@
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//
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// Copyright 2024 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: fft_reorder
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//
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// Description:
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//
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// This module optionally rearranges the order of FFT bins to put them in the
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// desired order. It also supports cyclic prefix insertion.
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//
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// The input order that this module receives is a parameter that must be
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// chosen at compile time. The following input orders are supported:
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//
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// NATURAL: Positive frequencies are input first, starting with 0 Hz,
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// followed by negative frequencies. Frequencies are input in
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// ascending order.
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// BIT_REVERSE: Like natural, but the bits of the indices are in reverse
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// order. For example, for a size 16 FFT, bin 0000 is input
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// first, followed by bin 1000, 0100, 1100, 0010, etc.
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//
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// The output order can be chosen at run time. The following output orders
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// are supported:
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//
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// NORMAL: Negative frequencies first, then positive frequencies. 0 Hz
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// is in the center. Frequencies are output in ascending order.
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// REVERSE: Reverse order of NORMAL. Positive frequencies first, then
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// negative frequencies. 0 Hz in the center. Frequencies are
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// output in descending order.
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// NATURAL: Positive frequencies are first, starting with 0 Hz,
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// followed by negative frequencies. Frequencies are output in
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// ascending order.
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// BIT_REVERSE: Like natural, but the bits of the indices are in reverse
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// order. For example, for a size 16 FFT, bin 0000 is output
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// first, followed by bin 1000, 0100, 1100, 0010, etc.
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//
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// Typically the FFT IP feeding this module will output data in BIT_REVERSE
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// order. The FFT IP may have an option to rearrange the data into NATURAL
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// order but enabling this feature causes a large memory to be added to the
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// IP to do the reordering. Since we want to also be able to provide NORMAL
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// order, and we don't want to add a second memory for that reordering, we do
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// all the reordering here in one memory.
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//
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// If the FFT core is outputting in the order you want, then this module
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// should probably be removed to save RAM and logic.
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//
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// The TLAST input/output corresponds to when the FFT input/output ends for a
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// single FFT-sized sequence of data. i_tlast must be asserted during the
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// last transfer of the input FFT to reset things for the next FFT input.
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//
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// For cyclic prefix insertion, the EN_CP_INSERTION parameter must be true
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// and i_tuser contains the cyclic prefix size to insert. It must be valid
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// during the first transfer of the packet. It can be any size from 0 to
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// 2**MAX_FFT_LEN_LOG2-1.
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//
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// Parameters:
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//
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// IN_FIFO_LOG2 : Log base-2 of the input FIFO size. Set to -1 to remove
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// the input FIFO. This FIFO is intended as a pipeline
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// stage to cut the timing path on the input.
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// OUT_FIFO_LOG2 : Log base-2 of the output FIFO size. This must be set to
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// at least 3.
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// INPUT_ORDER : BIT_REVERSE or NATURAL. See fft_reorder_pkg for values.
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// MAX_FFT_LEN_LOG2 : Ceiling of log base-2 of the maximum FFT size to be
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// supported.
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// DATA_W : Data width. Typically 32 for sc16 data type.
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// EN_CP_INSERTION : Controls whether or not the CP insertion logic is
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// included.
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//
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// Signals:
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//
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// i_t* : AXI-Stream data input. Each packet is one FFT to be processed. The
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// length of the packet must match the FFT size. i_tuser contains the
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// cyclic prefix size to insert for this packet and must be valid
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// during the first transfer of the packet.
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// o_t* : AXI-Stream data output. Each packet is one FFT with optional cyclic
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// prefix.
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//
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`default_nettype none
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module fft_reorder
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import fft_reorder_pkg::*;
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#(
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parameter int IN_FIFO_LOG2 = 1,
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parameter int OUT_FIFO_LOG2 = 3,
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parameter fft_order_t INPUT_ORDER = BIT_REVERSE,
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parameter int MAX_FFT_LEN_LOG2 = 12,
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parameter int DATA_W = 32,
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parameter bit EN_CP_INSERTION = 1,
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localparam int FFT_LEN_LOG2_W = $clog2(MAX_FFT_LEN_LOG2+1),
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localparam int CP_LEN_W = MAX_FFT_LEN_LOG2
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) (
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input wire clk,
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input wire rst,
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input wire fft_cfg_wr,
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input wire [FFT_LEN_LOG2_W-1:0] fft_len_log2,
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input fft_order_t fft_out_order,
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// Data Input
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input wire [ DATA_W-1:0] i_tdata,
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input wire [CP_LEN_W-1:0] i_tuser,
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input wire i_tlast,
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input wire i_tvalid,
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output wire i_tready,
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// Data Output
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output wire [DATA_W-1:0] o_tdata,
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output wire o_tlast,
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output wire o_tvalid,
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input wire o_tready
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);
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// These registers track if the current read/write buffers are OK to use
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logic ok_to_write = 1'b1; // Current write buffer is free for writes
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logic ok_to_read = 1'b0; // Current read buffer has data to read
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//---------------------------------------------------------------------------
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// Optional Data Input Pipeline
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//---------------------------------------------------------------------------
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logic [ DATA_W-1:0] in_fifo_o_tdata;
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logic [CP_LEN_W-1:0] in_fifo_o_tuser;
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logic in_fifo_o_tvalid;
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logic in_fifo_o_tready;
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logic in_fifo_o_tlast;
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if (IN_FIFO_LOG2 >= 0) begin : gen_in_fifo
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axi_fifo #(
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.WIDTH(1 + CP_LEN_W + DATA_W),
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.SIZE (IN_FIFO_LOG2)
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) axi_fifo_in (
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.clk (clk),
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.reset (rst),
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.clear ('0),
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.i_tdata ({i_tlast, i_tuser, i_tdata}),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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.o_tdata ({in_fifo_o_tlast, in_fifo_o_tuser, in_fifo_o_tdata}),
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.o_tvalid(in_fifo_o_tvalid),
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.o_tready(in_fifo_o_tready),
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.space (),
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.occupied()
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);
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end else begin : gen_no_in_fifo
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assign in_fifo_o_tdata = i_tdata;
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assign in_fifo_o_tuser = i_tuser;
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assign in_fifo_o_tlast = i_tlast;
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assign in_fifo_o_tvalid = i_tvalid;
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assign i_tready = in_fifo_o_tready;
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end
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//---------------------------------------------------------------------------
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// Optional Data Output Pipeline
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//---------------------------------------------------------------------------
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if (OUT_FIFO_LOG2 < 3) begin
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OUT_FIFO_LOG2_must_be_at_least_3();
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end
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logic [DATA_W-1:0] out_fifo_i_tdata;
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logic out_fifo_i_tvalid;
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logic out_fifo_i_tlast;
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// We use out_fifo_space instead of out_fifo_i_tready to allow extra space
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// for the RAM output read delay.
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logic [15:0] out_fifo_space;
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axi_fifo #(
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.WIDTH(DATA_W+1),
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.SIZE (OUT_FIFO_LOG2)
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) axi_fifo_out (
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.clk (clk),
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.reset (rst),
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.clear ('0),
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.i_tdata ({out_fifo_i_tlast, out_fifo_i_tdata}),
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.i_tvalid(out_fifo_i_tvalid),
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.i_tready(),
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.o_tdata ({o_tlast, o_tdata}),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready),
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.space (out_fifo_space),
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.occupied()
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);
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//---------------------------------------------------------------------------
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// Configuration Registers
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//---------------------------------------------------------------------------
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//
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// Store relevant FFT configuration values in registers for use elsewhere. We
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// assume that the configuration is set in advance of any operation and is
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// only changed when the FFT is idle, so we ignore the latency here.
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//
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//---------------------------------------------------------------------------
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// Number of bits needed to represent the maximum FFT size
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localparam FFT_LEN_W = MAX_FFT_LEN_LOG2+1;
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logic fft_cfg_wr_stb = 1'b0;
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fft_order_t fft_out_order_reg = NORMAL;
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logic [FFT_LEN_LOG2_W-1:0] fft_len_log2_reg = MAX_FFT_LEN_LOG2;
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logic [FFT_LEN_W-1:0] fft_len = 1 << MAX_FFT_LEN_LOG2;
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logic [FFT_LEN_W-1:0] fft_len_m1 = (1 << MAX_FFT_LEN_LOG2)-1;
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always_ff @(posedge clk) begin
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if(rst) begin
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fft_cfg_wr_stb <= 1'b0;
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fft_out_order_reg <= NORMAL;
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fft_len_log2_reg <= MAX_FFT_LEN_LOG2;
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fft_len <= 1 << MAX_FFT_LEN_LOG2;
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fft_len_m1 <= (1 << MAX_FFT_LEN_LOG2)-1;
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end else begin
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fft_cfg_wr_stb <= 1'b0;
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if (fft_cfg_wr) begin
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fft_cfg_wr_stb <= 1'b1;
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fft_out_order_reg <= fft_out_order;
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fft_len_log2_reg <= fft_len_log2;
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fft_len <= (1 << fft_len_log2);
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fft_len_m1 <= (1 << fft_len_log2)-1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// RAM Buffer
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//---------------------------------------------------------------------------
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//
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// This RAM stores the data that's being input, writing it the order needed
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// such that when read out sequentially, it will be in the correct order.
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//
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// The RAM is divided into two halves, which we'll call buffers. Each buffer
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// is used exclusively for read or write, until they switch.
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//
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//---------------------------------------------------------------------------
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// Address width for each buffer. Must be big enough to store the maximum
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// length FFT.
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localparam ADDR_W = MAX_FFT_LEN_LOG2;
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// RAM read latency
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localparam READ_LATENCY = 2;
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logic ram_rd_buffer; // Indicates which buffer is currently used for reads
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logic ram_wr_buffer; // Indicates which buffer is currently used for writes
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logic ram_wr_en;
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logic ram_wr_en_0; // One RAM read enable for each buffer
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logic ram_wr_en_1;
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logic [ADDR_W-1:0] ram_wr_addr;
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logic [DATA_W-1:0] ram_wr_data;
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logic ram_rd_en;
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logic [ADDR_W-1:0] ram_rd_addr;
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logic [DATA_W-1:0] ram_rd_data_raw_0; // One RAM read output for each buffer
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logic [DATA_W-1:0] ram_rd_data_raw_1;
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ram_2port #(
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.DWIDTH (DATA_W),
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.AWIDTH (ADDR_W), // Make the RAM two buffers big
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.OUT_REG(1)
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) ram_2port_0 (
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.clka (clk),
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.ena ('1),
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.wea (ram_wr_en_0),
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.addra(ram_wr_addr),
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.dia (ram_wr_data),
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.doa (),
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.clkb (clk),
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.enb ('1),
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.web ('0),
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.addrb(ram_rd_addr),
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.dib ('0),
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.dob (ram_rd_data_raw_0)
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);
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ram_2port #(
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.DWIDTH (DATA_W),
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.AWIDTH (ADDR_W), // Make the RAM two buffers big
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.OUT_REG(1)
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) ram_2port_1 (
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.clka (clk),
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.ena ('1),
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.wea (ram_wr_en_1),
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.addra(ram_wr_addr),
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.dia (ram_wr_data),
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.doa (),
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.clkb (clk),
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.enb ('1),
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.web ('0),
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.addrb(ram_rd_addr),
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.dib ('0),
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.dob (ram_rd_data_raw_1)
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);
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//---------------------------------------------------------------------------
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// Write Logic
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//---------------------------------------------------------------------------
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//
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// Here we write the data into the memory in a carefully controlled order
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// such that we can read it out in sequential or bit-reversed order to get
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// the order we want.
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//
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//---------------------------------------------------------------------------
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logic [FFT_LEN_W-1:0] fft_addr_mask;
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logic [FFT_LEN_W-1:0] wr_count;
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logic ram_wr_last;
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assign ram_wr_data = in_fifo_o_tdata;
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assign ram_wr_en = in_fifo_o_tvalid && in_fifo_o_tready;
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assign ram_wr_en_0 = ram_wr_en && (ram_wr_buffer == 1'b0);
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assign ram_wr_en_1 = ram_wr_en && (ram_wr_buffer == 1'b1);
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assign in_fifo_o_tready = ok_to_write;
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assign ram_wr_last = in_fifo_o_tlast;
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always_ff @(posedge clk) begin
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if (fft_cfg_wr_stb || (ram_wr_en && ram_wr_last)) begin
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if (fft_out_order_reg == NATURAL) begin
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// Natural to natural. No mask needed to affect the order.
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fft_addr_mask <= '0;
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ram_wr_addr <= '0;
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end else if (fft_out_order_reg == REVERSE) begin
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// Natural to reverse. Invert all bits except the MSB. Inverting the
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// lower bits reverses the order. Leaving the MSB unchanged ensures we
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// output positive frequencies first, then negative frequencies.
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fft_addr_mask <= fft_len_m1 >> 1; // e.g., 8'b0111_1111
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ram_wr_addr <= fft_len_m1 >> 1;
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end else if (fft_out_order_reg == NORMAL) begin
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// Natural to normal. Invert the MSB, so that we output negative
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// frequencies first, then positive frequencies.
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fft_addr_mask <= fft_len >> 1; // e.g., 8'b1000_0000
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ram_wr_addr <= fft_len >> 1;
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end else begin // (fft_order_t == BIT_REVERSE)
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// Natural to bit-reverse. For this we also use natural order, and we
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// enable/disable the bit-reversal on the read side as needed.
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fft_addr_mask <= '0;
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ram_wr_addr <= '0;
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end
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end
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if (ram_wr_en) begin
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wr_count <= wr_count+1;
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if (ram_wr_last) begin
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// Switch to the other buffer
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ram_wr_buffer <= ~ram_wr_buffer;
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wr_count <= '0;
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end else begin
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// Calculate the the next write address
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if (
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(INPUT_ORDER == BIT_REVERSE && fft_out_order_reg != BIT_REVERSE) ||
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(INPUT_ORDER == NATURAL && fft_out_order_reg == BIT_REVERSE)
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) begin : bit_reversed
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// If the input is bit-reversed and we're not outputting
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// bit-reversed, then we bit reverse the RAM address to convert from
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// bit-reversed to natural order. Then apply the mask to that to
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// convert from natural to the desired output order.
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ram_wr_addr <= bit_reverse(wr_count+1, fft_len_log2_reg) ^ fft_addr_mask;
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end else begin : natural
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// Apply the mask to convert from natural to to the desired output
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// order.
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ram_wr_addr <= (wr_count+1) ^ fft_addr_mask;
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end
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end
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end
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if (rst) begin
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ram_wr_buffer <= '0;
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ram_wr_addr <= '0;
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wr_count <= '0;
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end
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end
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//---------------------------------------------------------------------------
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// CP Insertion Length FIFO
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//---------------------------------------------------------------------------
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// Cyclic prefix logic interface signals
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logic cp_valid; // Indicates the CP FIFO has an output
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logic cp_non_zero; // Indicates the CP value is > 0
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logic [ADDR_W-1:0] cp_start_addr; // Indicates the CP RAM start address
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logic cp_consume; // Control to indicate we've captured the CP length output
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if (EN_CP_INSERTION) begin: gen_cp_ins_fifo
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logic [CP_LEN_W-1:0] cp_len_tdata;
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logic cp_len_tvalid;
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logic cp_len_tready;
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logic i_tvalid;
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logic in_fifo_o_tfirst = '1; // First transfer of packet
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// Create a register that indicates when the next transfer is the start of
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// a new packet.
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always_ff @(posedge clk) begin
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if (rst) begin
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in_fifo_o_tfirst <= '1;
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end else begin
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if (in_fifo_o_tvalid && in_fifo_o_tready) begin
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in_fifo_o_tfirst <= in_fifo_o_tlast;
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end
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end
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end
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// Write the first tuser word of the packet into the CP length FIFO
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assign i_tvalid = in_fifo_o_tvalid && in_fifo_o_tready && in_fifo_o_tfirst;
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// The dual RAM buffer can only hold two FFTs at a time, so we can
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// guarantee this FIFO has sufficient room and will always be ready by
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// setting its size appropriately.
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axi_fifo #(
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.WIDTH(CP_LEN_W),
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.SIZE (1)
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) axi_fifo_cp_length (
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.clk (clk),
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.reset (rst),
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.clear ('0),
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.i_tdata (in_fifo_o_tuser),
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.i_tvalid(i_tvalid),
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.i_tready(),
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.o_tdata (cp_len_tdata),
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.o_tvalid(cp_len_tvalid),
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||||
.o_tready(cp_consume),
|
||||
.space (),
|
||||
.occupied()
|
||||
);
|
||||
|
||||
// Add a register to calculate the cyclic prefix start read address and
|
||||
// figure out if we need to do a cyclic prefix insertion. The latency of
|
||||
// this register will be much less than the FFT write time.
|
||||
always_ff @(posedge clk) begin
|
||||
cp_valid <= cp_len_tvalid;
|
||||
cp_non_zero <= (cp_len_tdata != 0);
|
||||
cp_start_addr <= fft_len - cp_len_tdata;
|
||||
end
|
||||
end else begin : gen_no_cp_ins_fifo
|
||||
assign cp_valid = '0;
|
||||
assign cp_non_zero = '0;
|
||||
assign cp_start_addr = '0;
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Read Logic
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
typedef enum logic [1:0] { READ_CHECK, READ_CP, READ_FFT} read_state_t;
|
||||
read_state_t read_state = EN_CP_INSERTION ? READ_CHECK : READ_FFT;
|
||||
read_state_t read_state_nx;
|
||||
|
||||
logic [ADDR_W-1:0] ram_rd_addr_nx;
|
||||
logic ram_rd_buffer_nx;
|
||||
logic ram_rd_last; // Indicates when ram_rd_en asserts for the last sample
|
||||
logic out_fifo_avail;
|
||||
|
||||
// Delayed versions of read signals to align with read output timing
|
||||
logic [READ_LATENCY-1:0] ram_rd_buffer_del;
|
||||
logic [READ_LATENCY-1:0] ram_rd_en_del;
|
||||
logic [READ_LATENCY-1:0] ram_rd_last_del;
|
||||
|
||||
logic [DATA_W-1:0] ram_rd_data;
|
||||
logic ram_rd_data_valid; // Indicates ram_rd_data has data
|
||||
logic ram_rd_data_last; // Indicates ram_rd_data is the last of the FFT
|
||||
|
||||
assign out_fifo_i_tdata = ram_rd_data;
|
||||
assign out_fifo_i_tvalid = ram_rd_data_valid;
|
||||
assign out_fifo_i_tlast = ram_rd_data_last;
|
||||
|
||||
always_ff @(posedge clk) begin : read_fsm_reg
|
||||
if (rst) begin
|
||||
read_state <= EN_CP_INSERTION ? READ_CHECK : READ_FFT;
|
||||
ram_rd_buffer <= '0;
|
||||
ram_rd_addr <= '0;
|
||||
ram_rd_buffer_del <= '0;
|
||||
ram_rd_en_del <= '0;
|
||||
ram_rd_last_del <= '0;
|
||||
ram_rd_data <= 'X;
|
||||
ram_rd_data_valid <= '0;
|
||||
ram_rd_data_last <= '0;
|
||||
out_fifo_avail <= '0;
|
||||
end else begin
|
||||
read_state <= read_state_nx;
|
||||
ram_rd_buffer <= ram_rd_buffer_nx;
|
||||
ram_rd_addr <= ram_rd_addr_nx;
|
||||
|
||||
// Pipeline the buffer selection, enable, and last to align with RAM output
|
||||
ram_rd_buffer_del <= (ram_rd_buffer_del << 1) | ram_rd_buffer;
|
||||
ram_rd_en_del <= (ram_rd_en_del << 1) | ram_rd_en;
|
||||
ram_rd_last_del <= (ram_rd_last_del << 1) | ram_rd_last;
|
||||
|
||||
// Select the RAM output that was used for the read
|
||||
ram_rd_data <= ram_rd_buffer_del[READ_LATENCY-1] ?
|
||||
ram_rd_data_raw_1 : ram_rd_data_raw_0;
|
||||
ram_rd_data_valid <= ram_rd_en_del[READ_LATENCY-1];
|
||||
ram_rd_data_last <= ram_rd_last_del[READ_LATENCY-1];
|
||||
|
||||
// Ensure there's enough room in the output FIFO to account for the
|
||||
// latency through the read logic.
|
||||
out_fifo_avail <= out_fifo_space > 4;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin : read_fsm_comb
|
||||
ram_rd_en = '0;
|
||||
ram_rd_last = '0;
|
||||
ram_rd_buffer_nx = ram_rd_buffer;
|
||||
ram_rd_addr_nx = ram_rd_addr;
|
||||
read_state_nx = read_state;
|
||||
cp_consume = '0;
|
||||
|
||||
case (read_state)
|
||||
READ_CHECK : begin
|
||||
// Wait until the next cyclic prefix is available and update the RAM
|
||||
// read address appropriately.
|
||||
if (cp_valid) begin
|
||||
cp_consume = '1;
|
||||
if (cp_non_zero) begin
|
||||
read_state_nx = READ_CP;
|
||||
ram_rd_addr_nx = cp_start_addr;
|
||||
end else begin
|
||||
read_state_nx = READ_FFT;
|
||||
ram_rd_addr_nx = '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
READ_CP : begin
|
||||
// Read out the cyclic prefix
|
||||
ram_rd_en = (ok_to_read && out_fifo_avail);
|
||||
if (ram_rd_en) begin
|
||||
if (ram_rd_addr == fft_len_m1) begin
|
||||
ram_rd_addr_nx = '0;
|
||||
read_state_nx = READ_FFT;
|
||||
end else begin
|
||||
ram_rd_addr_nx = ram_rd_addr + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
default : begin // READ_FFT
|
||||
// Read out the whole FFT
|
||||
ram_rd_en = (ok_to_read && out_fifo_avail);
|
||||
if (ram_rd_en) begin
|
||||
if (ram_rd_addr == fft_len_m1) begin
|
||||
ram_rd_last = '1;
|
||||
ram_rd_addr_nx = '0;
|
||||
ram_rd_buffer_nx = ~ram_rd_buffer;
|
||||
read_state_nx = EN_CP_INSERTION ? READ_CHECK : READ_FFT;
|
||||
end else begin
|
||||
ram_rd_addr_nx = ram_rd_addr + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Read/Write Arbitration Logic
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// Here we ensure that we only write when the write buffer is free and that
|
||||
// we only read when the read buffer has an FFT in it. Because we're reading
|
||||
// and writing simultaneously, we swap between the lower and upper parts of
|
||||
// the RAM as data gets written and read out.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (ram_wr_en && ram_rd_en) begin
|
||||
if (ram_wr_last && ram_rd_last) begin
|
||||
// Both buffers are switching on the same cycle
|
||||
ok_to_write <= 1'b1;
|
||||
ok_to_read <= 1'b1;
|
||||
end else if (ram_wr_last) begin
|
||||
// Switching write buffer to the one being used for reads
|
||||
ok_to_write <= 1'b0;
|
||||
end else if (ram_rd_last) begin
|
||||
// Switching read buffer to the one being used for writes
|
||||
ok_to_read <= 1'b0;
|
||||
end
|
||||
end else if (ram_wr_en && ram_wr_last) begin
|
||||
// Write buffer is switching
|
||||
if (ram_wr_buffer == ram_rd_buffer) begin
|
||||
// Write buffer is switching away from the current read buffer
|
||||
ok_to_write <= 1'b1;
|
||||
ok_to_read <= 1'b1;
|
||||
end else begin
|
||||
// Write buffer is switching to the current read buffer
|
||||
ok_to_write <= 1'b0;
|
||||
end
|
||||
end else if (ram_rd_en && ram_rd_last) begin
|
||||
// Read buffer is switching
|
||||
if (ram_wr_buffer == ram_rd_buffer) begin
|
||||
// Read buffer is switching away from the current write buffer
|
||||
ok_to_write <= 1'b1;
|
||||
ok_to_read <= 1'b1;
|
||||
end else begin
|
||||
// Read buffer is switching to the current write buffer
|
||||
ok_to_read <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis translate_off
|
||||
if (ram_wr_en && ram_rd_en && (ram_wr_buffer == ram_rd_buffer)) begin
|
||||
$error("Attempt to read and write the same buffer!");
|
||||
end
|
||||
//synthesis translate_on
|
||||
|
||||
if (rst) begin
|
||||
ok_to_write <= 1'b1; // Buffers empty after reset
|
||||
ok_to_read <= 1'b0; // Can't read until we fill the first buffer
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Reference in New Issue
Block a user