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fpga: rfnoc: Add new FFT block

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This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.


Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
This commit is contained in:
Wade Fife
2024-12-17 22:13:42 +01:00
committed by Jörg Hofrichter
parent 0770fd4405
commit 81f150213f
20 changed files with 5256 additions and 963 deletions
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lib/rfnoc/blocks/rfnoc_block_fft/Makefile
+25 -8
View File
@@ -1,5 +1,5 @@
#
# Copyright 2019 Ettus Research, a National Instruments Brand
# Copyright 2024 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
@@ -21,17 +21,32 @@ LIB_IP_DIR = $(BASE_DIR)/../lib/ip
# Include makefiles and sources for all IP components
# *after* defining the LIB_IP_DIR
include $(LIB_IP_DIR)/axi_fft/Makefile.inc
include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc
include $(LIB_IP_DIR)/xfft_64k_16b/Makefile.inc
include $(LIB_IP_DIR)/xfft_32k_16b/Makefile.inc
include $(LIB_IP_DIR)/xfft_16k_16b/Makefile.inc
include $(LIB_IP_DIR)/xfft_8k_16b/Makefile.inc
include $(LIB_IP_DIR)/xfft_4k_16b/Makefile.inc
include $(LIB_IP_DIR)/xfft_2k_16b/Makefile.inc
include $(LIB_IP_DIR)/xfft_1k_16b/Makefile.inc
include $(LIB_IP_DIR)/complex_to_magphase_int17/Makefile.inc
DESIGN_SRCS += $(abspath \
$(LIB_IP_AXI_FFT_OUTS) \
$(LIB_IP_XFFT_64K_16B_OUTS) \
$(LIB_IP_XFFT_32K_16B_OUTS) \
$(LIB_IP_XFFT_16K_16B_OUTS) \
$(LIB_IP_XFFT_8K_16B_OUTS) \
$(LIB_IP_XFFT_4K_16B_OUTS) \
$(LIB_IP_XFFT_3K_16B_OUTS) \
$(LIB_IP_XFFT_2K_16B_OUTS) \
$(LIB_IP_XFFT_1K_16B_OUTS) \
$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS) \
)
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Include makefiles and sources for the DUT and its dependencies
# Include makefiles and sources for the DUT and its
# dependencies.
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
include Makefile.srcs
@@ -45,10 +60,12 @@ $(RFNOC_OOT_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
SIM_TOP = rfnoc_block_fft_tb glbl
SIM_SRCS = \
$(abspath rfnoc_block_fft_tb.sv) \
SIM_TOP = rfnoc_block_fft_all_tb glbl
SIM_SRCS = $(abspath \
rfnoc_block_fft_tb.sv \
rfnoc_block_fft_all_tb.sv \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
)
#-------------------------------------------------
# Bottom-of-Makefile