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fpga: lib: Add PHASE parameter to sim_clk_gen

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Original-commit: f6f43baa0012a24ed5a8cdf49240e0cb4a1f7d04
This commit is contained in:
Wade Fife
2021-06-03 11:26:54 -05:00
committed by Aaron Rossetto
parent 8cb9bdd331
commit 7fda8365de
1 changed files with 3 additions and 1 deletions
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sim/rfnoc/sim_clock_gen.sv
+3 -1
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@@ -15,7 +15,8 @@
module sim_clock_gen #( module sim_clock_gen #(
parameter realtime PERIOD = 10.0, // Period in ns parameter realtime PERIOD = 10.0, // Period in ns
parameter real DUTY_CYCLE = 0.5, // Duty cycle, in the range (0.0, 1.0) parameter real DUTY_CYCLE = 0.5, // Duty cycle, in the range (0.0, 1.0)
parameter bit AUTOSTART = 1 // Start clock automatically at time 0 parameter bit AUTOSTART = 1, // Start clock automatically at time 0
parameter realtime PHASE = 0.0 // Phase offset
) ( ) (
output bit clk, output bit clk,
output bit rst output bit rst
@@ -112,6 +113,7 @@ module sim_clock_gen #(
//-------------------------- //--------------------------
initial begin : clock_block initial begin : clock_block
if (PHASE != 0.0) #(PHASE);
// Toggle the clock in a loop // Toggle the clock in a loop
forever begin : clock_loop forever begin : clock_loop
#(low_time); #(low_time);