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fpga: e320: Update AXI interconnect address range

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This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: d352f5a9c3bd3791f0320be1e615146fe7459453
This commit is contained in:
Wade Fife
2020-08-28 15:07:38 -05:00
parent cf524e9af5
commit 7e3f04d0ab
2 changed files with 1373 additions and 2195 deletions
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top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd
+1368 -2191
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File diff suppressed because it is too large Load Diff
top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
+5 -4
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@@ -1,10 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="33"> <Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="axi_intercon_4x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true"> <CompositeFile CompositeFileTopName="axi_intercon_4x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description> <Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/> <Generation Name="SYNTHESIS" State="STALE" Timestamp="1591253143"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/> <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/> <Generation Name="SIMULATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1591253143"/>
<FileCollection Name="SOURCES" Type="SOURCES"> <FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/axi_intercon_4x64_256_bd_m00_rs_0/axi_intercon_4x64_256_bd_m00_rs_0.xci" Type="IP"> <File Name="ip/axi_intercon_4x64_256_bd_m00_rs_0/axi_intercon_4x64_256_bd_m00_rs_0.xci" Type="IP">
<Instance HierarchyPath="m00_rs"/> <Instance HierarchyPath="m00_rs"/>