fpga: lib: Fix comments and indentation in axi_fifo_short.v

Original-commit: da3af4e6e86809038872a61696f3d1bac2e8583c

lib/fifo/axi_fifo_short.v

@@ -1,21 +1,19 @@
 //
 // Copyright 2012 Ettus Research LLC
 // Copyright 2018 Ettus Research, a National Instruments Company
+// Copyright 2020 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
-
+// Description: 32 word FIFO with AXI4-Stream interface.
-
 //
-// 32 word FIFO with AXI4-STREAM interface.
+// NOTE: This module uses the SRLC32E primitive explicitly and as such can
-//
+// only be used with Xilinx technology.
-// NOTE: This module uses the SRLC32E primitive explicitly and as such
-// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
 //
 
-module axi_fifo_short
+module axi_fifo_short #(
-  #(parameter WIDTH=32)
+  parameter WIDTH = 32
-   (
+) (
   input              clk,
   input              reset,
   input              clear,
@@ -41,55 +39,45 @@ module axi_fifo_short
   genvar i; 
   
   generate
-      for (i=0;i<WIDTH;i=i+1)
+    for (i=0;i<WIDTH;i=i+1) begin : gen_srlc32e
-	begin : gen_srlc32e
+      SRLC32E srlc32e(
-	   SRLC32E
+        .Q(o_tdata[i]), .Q31(),
-	     srlc32e(.Q(o_tdata[i]), .Q31(),
+        .A(a),
-		     .A(a), //.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),.A4(a[4]),
+        .CE(write),.CLK(clk),.D(i_tdata[i])
-		    .CE(write),.CLK(clk),.D(i_tdata[i]));
+      );
     end
   endgenerate
   
-   always @(posedge clk)
+  always @(posedge clk) begin
-     if(reset)
+    if(reset) begin
-       begin
        a <= 0;
        empty <= 1;
        full <= 0;
     end
-     else if(clear)
+    else if(clear) begin
-       begin
       a <= 0;
       empty <= 1;
       full<= 0;
     end
-     else if(read & ~write)
+    else if(read & ~write) begin
-       begin
       full <= 0;
       if(a==0)
         empty <= 1;
       else
         a <= a - 1;
     end
-     else if(write & ~read)
+    else if(write & ~read) begin
-       begin
       empty <= 0;
       if(~empty)
         a <= a + 1;
       if(a == 30)
         full <= 1;
     end
+  end
 
-   // NOTE will fail if you write into a full fifo or read from an empty one
+  // NOTE: Will fail if you write into a full FIFO or read from an empty one
 
-   //////////////////////////////////////////////////////////////
+  always @(posedge clk) begin
-   // space and occupied are used for diagnostics, not 
-   // guaranteed correct
-   
-   //assign space = full ? 0 : empty ? 16 : 15-a;
-   //assign occupied = empty ? 0 : full ? 16 : a+1;
-
-   always @(posedge clk)
     if(reset)
       space <= 6'd32;
     else if(clear)
@@ -98,8 +86,9 @@ module axi_fifo_short
       space <= space + 6'd1;
     else if(write & ~read)
       space <= space - 6'd1;
+  end
   
-   always @(posedge clk)
+  always @(posedge clk) begin
     if(reset)
       occupied <= 6'd0;
     else if(clear)
@@ -108,6 +97,6 @@ module axi_fifo_short
       occupied <= occupied - 6'd1;
     else if(write & ~read)
       occupied <= occupied + 6'd1;
+  end
     
 endmodule // axi_fifo_short
-