Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd

top/x300/coregen_dsp/hb63.coe

@@ -1,67 +0,0 @@
-; Generated with round((2^18-2)*halfgen_test(.22,16,1))
-;  88% effective BW, 64dB to 87dB rolloff
-Radix=10;
-CoefData = 
--35,
- 0,
- 95,
- 0,
--195,
- 0,
- 352,
- 0,
--582,
- 0,
- 907,
- 0,
--1354,
- 0,
- 1953,
- 0,
--2751,
- 0,
- 3813,
- 0,
--5249,
- 0,
- 7264,
- 0,
--10296,
- 0,
- 15494,
- 0,
--27083,
- 0,
- 83196,
- 131071,
- 83196,
- 0,
--27083,
- 0,
- 15494,
- 0,
--10296,
- 0,
- 7264,
- 0,
--5249,
- 0,
- 3813,
- 0,
--2751,
- 0,
- 1953,
- 0,
--1354,
- 0,
- 907,
- 0,
--582,
- 0,
- 352,
- 0,
- -195,
- 0
- 95,
- 0
--35;