Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,9 +0,0 @@
-SET busformat = BusFormatAngleBracketNotRipped
-SET designentry = Verilog
-SET device = xc7k410t
-SET devicefamily = kintex7
-SET flowvendor = Other
-SET package = ffg900
-SET speedgrade = -2
-SET verilogsim = true
-SET vhdlsim = false