Removed copy of FPGA source files.
Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
@@ -1,4 +0,0 @@
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||||
_xmsgs
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||||
*.log
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||||
*.ncf
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||||
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||||
@@ -1 +0,0 @@
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||||
fir_compiler_v5_0
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||||
@@ -1,23 +0,0 @@
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||||
#
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# Copyright 2012 Ettus Research LLC
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||||
#
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||||
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||||
##################################################
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# Coregen Sources
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##################################################
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COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x300/coregen_dsp/, \
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hbdec1.v \
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hbdec1.xco \
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hbdec2.v \
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hbdec2.xco \
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hbdec3.v \
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hbdec3.xco \
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hbint1.v \
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||||
hbint1.xco \
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hbint2.v \
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hbint2.xco \
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hbint3.v \
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hbint3.xco \
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))
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@@ -1,9 +0,0 @@
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||||
SET busformat = BusFormatAngleBracketNotRipped
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||||
SET designentry = Verilog
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||||
SET device = xc7k410t
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||||
SET devicefamily = kintex7
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||||
SET flowvendor = Other
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||||
SET package = ffg900
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||||
SET speedgrade = -2
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||||
SET verilogsim = true
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||||
SET vhdlsim = false
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||||
@@ -1,36 +0,0 @@
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||||
Radix=10;
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||||
CoefData = 282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
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||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
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||||
65536,
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||||
41478,
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||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282;
|
||||
@@ -1,32 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = -581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
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0,
|
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-4434,
|
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-0,
|
||||
2814,
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0,
|
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-1759,
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||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581;
|
||||
@@ -1,36 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = 282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282;
|
||||
@@ -1,40 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = -102,
|
||||
0,
|
||||
282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282,
|
||||
0,
|
||||
-102;
|
||||
@@ -1,44 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = 100,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
100;
|
||||
@@ -1,51 +0,0 @@
|
||||
; Generated with round((2^18-2)*halfgen_test(.21,12,1))
|
||||
; 83% effective BW, 64dB to 85dB rolloff
|
||||
Radix=10;
|
||||
CoefData =
|
||||
-62,
|
||||
0,
|
||||
194,
|
||||
0,
|
||||
-440,
|
||||
0,
|
||||
855,
|
||||
0,
|
||||
-1505,
|
||||
0,
|
||||
2478,
|
||||
0,
|
||||
-3900,
|
||||
0,
|
||||
5990,
|
||||
0,
|
||||
-9187,
|
||||
0,
|
||||
14632,
|
||||
0,
|
||||
-26536,
|
||||
0,
|
||||
83009,
|
||||
131071,
|
||||
83009,
|
||||
0,
|
||||
-26536,
|
||||
0,
|
||||
14632,
|
||||
0,
|
||||
-9187,
|
||||
0,
|
||||
5990,
|
||||
0,
|
||||
-3900,
|
||||
0,
|
||||
2478,
|
||||
0,
|
||||
-1505,
|
||||
0,
|
||||
855,
|
||||
0,
|
||||
-440,
|
||||
0
|
||||
194,
|
||||
0,
|
||||
-62;
|
||||
@@ -1,52 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = 300,
|
||||
0,
|
||||
-200,
|
||||
0,
|
||||
100,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
100,
|
||||
0,
|
||||
-200,
|
||||
0,
|
||||
300;
|
||||
@@ -1,56 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = -400,
|
||||
0,
|
||||
300,
|
||||
0,
|
||||
-200,
|
||||
0,
|
||||
100,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
100,
|
||||
0,
|
||||
-200,
|
||||
0,
|
||||
300,
|
||||
0,
|
||||
-400;
|
||||
@@ -1,60 +0,0 @@
|
||||
Radix=10;
|
||||
CoefData = 500,
|
||||
0,
|
||||
-400,
|
||||
0,
|
||||
300,
|
||||
0,
|
||||
-200,
|
||||
0,
|
||||
100,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
282,
|
||||
-0,
|
||||
-581,
|
||||
0,
|
||||
1053,
|
||||
-0,
|
||||
-1759,
|
||||
0,
|
||||
2814,
|
||||
-0,
|
||||
-4434,
|
||||
0,
|
||||
7193,
|
||||
-0,
|
||||
-13190,
|
||||
0,
|
||||
41478,
|
||||
65536,
|
||||
41478,
|
||||
0,
|
||||
-13190,
|
||||
-0,
|
||||
7193,
|
||||
0,
|
||||
-4434,
|
||||
-0,
|
||||
2814,
|
||||
0,
|
||||
-1759,
|
||||
-0,
|
||||
1053,
|
||||
0,
|
||||
-581,
|
||||
-0,
|
||||
282,
|
||||
0,
|
||||
-102,
|
||||
0,
|
||||
100,
|
||||
0,
|
||||
-200,
|
||||
0,
|
||||
300,
|
||||
0,
|
||||
-400,
|
||||
0
|
||||
500;
|
||||
@@ -1,67 +0,0 @@
|
||||
; Generated with round((2^18-2)*halfgen_test(.22,16,1))
|
||||
; 88% effective BW, 64dB to 87dB rolloff
|
||||
Radix=10;
|
||||
CoefData =
|
||||
-35,
|
||||
0,
|
||||
95,
|
||||
0,
|
||||
-195,
|
||||
0,
|
||||
352,
|
||||
0,
|
||||
-582,
|
||||
0,
|
||||
907,
|
||||
0,
|
||||
-1354,
|
||||
0,
|
||||
1953,
|
||||
0,
|
||||
-2751,
|
||||
0,
|
||||
3813,
|
||||
0,
|
||||
-5249,
|
||||
0,
|
||||
7264,
|
||||
0,
|
||||
-10296,
|
||||
0,
|
||||
15494,
|
||||
0,
|
||||
-27083,
|
||||
0,
|
||||
83196,
|
||||
131071,
|
||||
83196,
|
||||
0,
|
||||
-27083,
|
||||
0,
|
||||
15494,
|
||||
0,
|
||||
-10296,
|
||||
0,
|
||||
7264,
|
||||
0,
|
||||
-5249,
|
||||
0,
|
||||
3813,
|
||||
0,
|
||||
-2751,
|
||||
0,
|
||||
1953,
|
||||
0,
|
||||
-1354,
|
||||
0,
|
||||
907,
|
||||
0,
|
||||
-582,
|
||||
0,
|
||||
352,
|
||||
0,
|
||||
-195,
|
||||
0
|
||||
95,
|
||||
0
|
||||
-35;
|
||||
@@ -1,61 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 hbdec1
|
||||
RECTANGLE Normal 32 32 544 2048
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName nd
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din_1[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName din_2[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName coef_ld
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 880 32 880
|
||||
PIN 0 880 LEFT 36
|
||||
PINATTR PinName coef_we
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName coef_din[17:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1008 32 1008
|
||||
PIN 0 1008 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName ce
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1072 32 1072
|
||||
PIN 0 1072 LEFT 36
|
||||
PINATTR PinName sclr
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 240 544 240
|
||||
PIN 576 240 RIGHT 36
|
||||
PINATTR PinName dout_1[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 272 544 272
|
||||
PIN 576 272 RIGHT 36
|
||||
PINATTR PinName dout_2[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1840 544 1840
|
||||
PIN 576 1840 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1872 544 1872
|
||||
PIN 576 1872 RIGHT 36
|
||||
PINATTR PinName rdy
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1904 544 1904
|
||||
PIN 576 1904 RIGHT 36
|
||||
PINATTR PinName data_valid
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbdec1.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbdec1.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbdec1.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbdec1_reload_order.txt" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
@@ -1,47 +0,0 @@
|
||||
111111111111000010
|
||||
000000000000000000
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
111111111001001000
|
||||
000000000000000000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
111111101000011111
|
||||
000000000000000000
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
111111000011000100
|
||||
000000000000000000
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
111101110000011101
|
||||
000000000000000000
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
111001100001011000
|
||||
000000000000000000
|
||||
010100010001000001
|
||||
011111111111111111
|
||||
010100010001000001
|
||||
000000000000000000
|
||||
111001100001011000
|
||||
000000000000000000
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
111101110000011101
|
||||
000000000000000000
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
111111000011000100
|
||||
000000000000000000
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
111111101000011111
|
||||
000000000000000000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
111111111001001000
|
||||
000000000000000000
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
111111111111000010
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -1,79 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
|
||||
* *
|
||||
* This file contains confidential and proprietary information *
|
||||
* of Xilinx, Inc. and is protected under U.S. and *
|
||||
* international copyright and other intellectual property *
|
||||
* laws. *
|
||||
* *
|
||||
* DISCLAIMER *
|
||||
* This disclaimer is not a license and does not grant any *
|
||||
* rights to the materials distributed herewith. Except as *
|
||||
* otherwise provided in a valid license issued to you by *
|
||||
* Xilinx, and to the maximum extent permitted by applicable *
|
||||
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
||||
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
||||
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
||||
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
||||
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, *
|
||||
* including negligence, or under any other theory of *
|
||||
* liability) for any loss or damage of any kind or nature *
|
||||
* related to, arising under or in connection with these *
|
||||
* materials, including for any direct, or any indirect, *
|
||||
* special, incidental, or consequential loss or damage *
|
||||
* (including loss of data, profits, goodwill, or any type of *
|
||||
* loss or damage suffered as a result of any action brought *
|
||||
* by a third party) even if such damage or loss was *
|
||||
* reasonably foreseeable or Xilinx had been advised of the *
|
||||
* possibility of the same. *
|
||||
* *
|
||||
* CRITICAL APPLICATIONS *
|
||||
* Xilinx products are not designed or intended to be fail- *
|
||||
* safe, or for use in any application requiring fail-safe *
|
||||
* performance, such as life-support or safety devices or *
|
||||
* systems, Class III medical devices, nuclear facilities, *
|
||||
* applications related to the deployment of airbags, or any *
|
||||
* other applications that could lead to death, personal *
|
||||
* injury, or severe property or environmental damage *
|
||||
* (individually and collectively, "Critical *
|
||||
* Applications"). Customer assumes the sole risk and *
|
||||
* liability of any use of Xilinx products in Critical *
|
||||
* Applications, subject only to applicable laws and *
|
||||
* regulations governing limitations on product liability. *
|
||||
* *
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
||||
* PART OF THIS FILE AT ALL TIMES. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hbdec1 YourInstanceName (
|
||||
.sclr(sclr), // input sclr
|
||||
.clk(clk), // input clk
|
||||
.ce(ce), // input ce
|
||||
.nd(nd), // input nd
|
||||
.coef_ld(coef_ld), // input coef_ld
|
||||
.coef_we(coef_we), // input coef_we
|
||||
.coef_din(coef_din), // input [17 : 0] coef_din
|
||||
.rfd(rfd), // output rfd
|
||||
.rdy(rdy), // output rdy
|
||||
.data_valid(data_valid), // output data_valid
|
||||
.din_1(din_1), // input [23 : 0] din_1
|
||||
.din_2(din_2), // input [23 : 0] din_2
|
||||
.dout_1(dout_1), // output [46 : 0] dout_1
|
||||
.dout_2(dout_2)); // output [46 : 0] dout_2
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hbdec1.v when simulating
|
||||
// the core, hbdec1. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,102 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Wed Dec 4 21:34:29 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fir_compiler:5.0
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k325t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET allow_rounding_approximation=false
|
||||
CSET bestprecision=false
|
||||
CSET chan_in_adv=0
|
||||
CSET clock_frequency=200.0
|
||||
CSET coefficient_buffer_type=Automatic
|
||||
CSET coefficient_file=./hb47.coe
|
||||
CSET coefficient_fractional_bits=0
|
||||
CSET coefficient_reload=true
|
||||
CSET coefficient_sets=1
|
||||
CSET coefficient_sign=Signed
|
||||
CSET coefficient_structure=Half_Band
|
||||
CSET coefficient_width=18
|
||||
CSET coefficientsource=COE_File
|
||||
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
|
||||
CSET columnconfig=7
|
||||
CSET component_name=hbdec1
|
||||
CSET data_buffer_type=Automatic
|
||||
CSET data_fractional_bits=0
|
||||
CSET data_sign=Signed
|
||||
CSET data_width=24
|
||||
CSET decimation_rate=2
|
||||
CSET displayreloadorder=false
|
||||
CSET filter_architecture=Systolic_Multiply_Accumulate
|
||||
CSET filter_selection=1
|
||||
CSET filter_type=Decimation
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET hardwareoversamplingrate=1
|
||||
CSET has_ce=true
|
||||
CSET has_data_valid=true
|
||||
CSET has_nd=true
|
||||
CSET has_sclr=true
|
||||
CSET input_buffer_type=Automatic
|
||||
CSET inter_column_pipe_length=4
|
||||
CSET interpolation_rate=1
|
||||
CSET multi_column_support=Disabled
|
||||
CSET number_channels=1
|
||||
CSET number_paths=2
|
||||
CSET optimization_goal=Area
|
||||
CSET output_buffer_type=Automatic
|
||||
CSET output_rounding_mode=Full_Precision
|
||||
CSET output_width=47
|
||||
CSET passband_max=0.5
|
||||
CSET passband_min=0.0
|
||||
CSET preference_for_other_storage=Automatic
|
||||
CSET quantization=Integer_Coefficients
|
||||
CSET rate_change_type=Integer
|
||||
CSET ratespecification=Frequency_Specification
|
||||
CSET registered_output=true
|
||||
CSET sample_frequency=200
|
||||
CSET sampleperiod=1
|
||||
CSET sclr_deterministic=true
|
||||
CSET stopband_max=1.0
|
||||
CSET stopband_min=0.5
|
||||
CSET usechan_in_adv=false
|
||||
CSET zero_pack_factor=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T05:23:34Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 8b63d7c7
|
||||
@@ -1,72 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="hbdec1.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="hbdec1.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbdec1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="hbdec1.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbdec1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbdec1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-04T13:35:30" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A940ACE469CBDB14A68CA6C88B3234B8" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,5 +0,0 @@
|
||||
111111111111000010
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,5 +0,0 @@
|
||||
111111111001001000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,5 +0,0 @@
|
||||
111111101000011111
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,5 +0,0 @@
|
||||
111111000011000100
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,5 +0,0 @@
|
||||
111101110000011101
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,5 +0,0 @@
|
||||
111001100001011000
|
||||
010100010001000001
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,3 +0,0 @@
|
||||
011111111111111111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,22 +0,0 @@
|
||||
# Output products list for <hbdec1>
|
||||
hbdec1.asy
|
||||
hbdec1.gise
|
||||
hbdec1.mif
|
||||
hbdec1.ngc
|
||||
hbdec1.v
|
||||
hbdec1.veo
|
||||
hbdec1.xco
|
||||
hbdec1.xise
|
||||
hbdec1COEFF_auto0_0.mif
|
||||
hbdec1COEFF_auto0_1.mif
|
||||
hbdec1COEFF_auto0_2.mif
|
||||
hbdec1COEFF_auto0_3.mif
|
||||
hbdec1COEFF_auto0_4.mif
|
||||
hbdec1COEFF_auto0_5.mif
|
||||
hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
hbdec1_flist.txt
|
||||
hbdec1_readme.txt
|
||||
hbdec1_reload_addrfilt_decode_rom.mif
|
||||
hbdec1_reload_order.txt
|
||||
hbdec1_xmdf.tcl
|
||||
hbdec1filt_decode_rom.mif
|
||||
@@ -1,67 +0,0 @@
|
||||
The following files were generated for 'hbdec1' in directory
|
||||
/home/matt/fpgadev/usrp3/top/x300/coregen_dsp/
|
||||
|
||||
Opens the IP Customization GUI:
|
||||
Allows the user to customize or recustomize the IP instance.
|
||||
|
||||
* hbdec1.mif
|
||||
* hbdec1_reload_order.txt
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* hbdec1.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* hbdec1.ngc
|
||||
* hbdec1.v
|
||||
* hbdec1.veo
|
||||
* hbdec1COEFF_auto0_0.mif
|
||||
* hbdec1COEFF_auto0_1.mif
|
||||
* hbdec1COEFF_auto0_2.mif
|
||||
* hbdec1COEFF_auto0_3.mif
|
||||
* hbdec1COEFF_auto0_4.mif
|
||||
* hbdec1COEFF_auto0_5.mif
|
||||
* hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
* hbdec1_reload_addrfilt_decode_rom.mif
|
||||
* hbdec1filt_decode_rom.mif
|
||||
|
||||
Creates an HDL instantiation template:
|
||||
Creates an HDL instantiation template for the IP.
|
||||
|
||||
* hbdec1.veo
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* hbdec1.asy
|
||||
* hbdec1.mif
|
||||
* hbdec1_reload_order.txt
|
||||
|
||||
Generate ISE metadata:
|
||||
Create a metadata file for use when including this core in ISE designs
|
||||
|
||||
* hbdec1_xmdf.tcl
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* hbdec1.gise
|
||||
* hbdec1.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* hbdec1_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* hbdec1_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
00
|
||||
10
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
@@ -1,25 +0,0 @@
|
||||
Reload index 0 = Index 20
|
||||
Reload index 1 = Index 22
|
||||
Reload index 2 = Index 16
|
||||
Reload index 3 = Index 18
|
||||
Reload index 4 = Index 12
|
||||
Reload index 5 = Index 14
|
||||
Reload index 6 = Index 8
|
||||
Reload index 7 = Index 10
|
||||
Reload index 8 = Index 4
|
||||
Reload index 9 = Index 6
|
||||
Reload index 10 = Index 0
|
||||
Reload index 11 = Index 2
|
||||
Reload index 12 = Index 23
|
||||
Reload index 13 = Index 0
|
||||
Reload index 14 = Index 0
|
||||
Reload index 15 = Index 0
|
||||
Reload index 16 = Index 0
|
||||
Reload index 17 = Index 0
|
||||
Reload index 18 = Index 0
|
||||
Reload index 19 = Index 0
|
||||
Reload index 20 = Index 0
|
||||
Reload index 21 = Index 0
|
||||
Reload index 22 = Index 0
|
||||
Reload index 23 = Index 0
|
||||
|
||||
@@ -1,111 +0,0 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide hbdec1_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::hbdec1_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::hbdec1_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1
|
||||
}
|
||||
# ::hbdec1_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::hbdec1_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -1,17 +0,0 @@
|
||||
00
|
||||
10
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
@@ -1,61 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 hbdec2
|
||||
RECTANGLE Normal 32 32 544 2048
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName nd
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din_1[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName din_2[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName coef_ld
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 880 32 880
|
||||
PIN 0 880 LEFT 36
|
||||
PINATTR PinName coef_we
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName coef_din[17:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1008 32 1008
|
||||
PIN 0 1008 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName ce
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1072 32 1072
|
||||
PIN 0 1072 LEFT 36
|
||||
PINATTR PinName sclr
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 240 544 240
|
||||
PIN 576 240 RIGHT 36
|
||||
PINATTR PinName dout_1[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 272 544 272
|
||||
PIN 576 272 RIGHT 36
|
||||
PINATTR PinName dout_2[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1840 544 1840
|
||||
PIN 576 1840 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1872 544 1872
|
||||
PIN 576 1872 RIGHT 36
|
||||
PINATTR PinName rdy
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1904 544 1904
|
||||
PIN 576 1904 RIGHT 36
|
||||
PINATTR PinName data_valid
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbdec2.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbdec2.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbdec2.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbdec2_reload_order.txt" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
@@ -1,47 +0,0 @@
|
||||
111111111111000010
|
||||
000000000000000000
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
111111111001001000
|
||||
000000000000000000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
111111101000011111
|
||||
000000000000000000
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
111111000011000100
|
||||
000000000000000000
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
111101110000011101
|
||||
000000000000000000
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
111001100001011000
|
||||
000000000000000000
|
||||
010100010001000001
|
||||
011111111111111111
|
||||
010100010001000001
|
||||
000000000000000000
|
||||
111001100001011000
|
||||
000000000000000000
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
111101110000011101
|
||||
000000000000000000
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
111111000011000100
|
||||
000000000000000000
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
111111101000011111
|
||||
000000000000000000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
111111111001001000
|
||||
000000000000000000
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
111111111111000010
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -1,79 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
|
||||
* *
|
||||
* This file contains confidential and proprietary information *
|
||||
* of Xilinx, Inc. and is protected under U.S. and *
|
||||
* international copyright and other intellectual property *
|
||||
* laws. *
|
||||
* *
|
||||
* DISCLAIMER *
|
||||
* This disclaimer is not a license and does not grant any *
|
||||
* rights to the materials distributed herewith. Except as *
|
||||
* otherwise provided in a valid license issued to you by *
|
||||
* Xilinx, and to the maximum extent permitted by applicable *
|
||||
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
||||
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
||||
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
||||
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
||||
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, *
|
||||
* including negligence, or under any other theory of *
|
||||
* liability) for any loss or damage of any kind or nature *
|
||||
* related to, arising under or in connection with these *
|
||||
* materials, including for any direct, or any indirect, *
|
||||
* special, incidental, or consequential loss or damage *
|
||||
* (including loss of data, profits, goodwill, or any type of *
|
||||
* loss or damage suffered as a result of any action brought *
|
||||
* by a third party) even if such damage or loss was *
|
||||
* reasonably foreseeable or Xilinx had been advised of the *
|
||||
* possibility of the same. *
|
||||
* *
|
||||
* CRITICAL APPLICATIONS *
|
||||
* Xilinx products are not designed or intended to be fail- *
|
||||
* safe, or for use in any application requiring fail-safe *
|
||||
* performance, such as life-support or safety devices or *
|
||||
* systems, Class III medical devices, nuclear facilities, *
|
||||
* applications related to the deployment of airbags, or any *
|
||||
* other applications that could lead to death, personal *
|
||||
* injury, or severe property or environmental damage *
|
||||
* (individually and collectively, "Critical *
|
||||
* Applications"). Customer assumes the sole risk and *
|
||||
* liability of any use of Xilinx products in Critical *
|
||||
* Applications, subject only to applicable laws and *
|
||||
* regulations governing limitations on product liability. *
|
||||
* *
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
||||
* PART OF THIS FILE AT ALL TIMES. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hbdec2 YourInstanceName (
|
||||
.sclr(sclr), // input sclr
|
||||
.clk(clk), // input clk
|
||||
.ce(ce), // input ce
|
||||
.nd(nd), // input nd
|
||||
.coef_ld(coef_ld), // input coef_ld
|
||||
.coef_we(coef_we), // input coef_we
|
||||
.coef_din(coef_din), // input [17 : 0] coef_din
|
||||
.rfd(rfd), // output rfd
|
||||
.rdy(rdy), // output rdy
|
||||
.data_valid(data_valid), // output data_valid
|
||||
.din_1(din_1), // input [23 : 0] din_1
|
||||
.din_2(din_2), // input [23 : 0] din_2
|
||||
.dout_1(dout_1), // output [46 : 0] dout_1
|
||||
.dout_2(dout_2)); // output [46 : 0] dout_2
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hbdec2.v when simulating
|
||||
// the core, hbdec2. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,102 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Wed Dec 4 21:33:01 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fir_compiler:5.0
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k325t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET allow_rounding_approximation=false
|
||||
CSET bestprecision=false
|
||||
CSET chan_in_adv=0
|
||||
CSET clock_frequency=200
|
||||
CSET coefficient_buffer_type=Automatic
|
||||
CSET coefficient_file=./hb47.coe
|
||||
CSET coefficient_fractional_bits=0
|
||||
CSET coefficient_reload=true
|
||||
CSET coefficient_sets=1
|
||||
CSET coefficient_sign=Signed
|
||||
CSET coefficient_structure=Half_Band
|
||||
CSET coefficient_width=18
|
||||
CSET coefficientsource=COE_File
|
||||
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
|
||||
CSET columnconfig=4
|
||||
CSET component_name=hbdec2
|
||||
CSET data_buffer_type=Automatic
|
||||
CSET data_fractional_bits=0
|
||||
CSET data_sign=Signed
|
||||
CSET data_width=24
|
||||
CSET decimation_rate=2
|
||||
CSET displayreloadorder=false
|
||||
CSET filter_architecture=Systolic_Multiply_Accumulate
|
||||
CSET filter_selection=1
|
||||
CSET filter_type=Decimation
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET hardwareoversamplingrate=1
|
||||
CSET has_ce=true
|
||||
CSET has_data_valid=true
|
||||
CSET has_nd=true
|
||||
CSET has_sclr=true
|
||||
CSET input_buffer_type=Automatic
|
||||
CSET inter_column_pipe_length=4
|
||||
CSET interpolation_rate=1
|
||||
CSET multi_column_support=Disabled
|
||||
CSET number_channels=1
|
||||
CSET number_paths=2
|
||||
CSET optimization_goal=Area
|
||||
CSET output_buffer_type=Automatic
|
||||
CSET output_rounding_mode=Full_Precision
|
||||
CSET output_width=47
|
||||
CSET passband_max=0.5
|
||||
CSET passband_min=0.0
|
||||
CSET preference_for_other_storage=Automatic
|
||||
CSET quantization=Integer_Coefficients
|
||||
CSET rate_change_type=Integer
|
||||
CSET ratespecification=Frequency_Specification
|
||||
CSET registered_output=true
|
||||
CSET sample_frequency=100
|
||||
CSET sampleperiod=1
|
||||
CSET sclr_deterministic=true
|
||||
CSET stopband_max=1.0
|
||||
CSET stopband_min=0.5
|
||||
CSET usechan_in_adv=false
|
||||
CSET zero_pack_factor=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T05:23:34Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: b27c3487
|
||||
@@ -1,72 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="hbdec2.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="hbdec2.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbdec2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="hbdec2.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbdec2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbdec2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-04T13:33:56" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8D4FB15FCAB64E0DEA10CDE0E19A7C80" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,9 +0,0 @@
|
||||
111111111111000010
|
||||
000000000011000010
|
||||
111111111001001000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,9 +0,0 @@
|
||||
111111101000011111
|
||||
000000100110101110
|
||||
111111000011000100
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,9 +0,0 @@
|
||||
111101110000011101
|
||||
000011100100101000
|
||||
111001100001011000
|
||||
010100010001000001
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,3 +0,0 @@
|
||||
011111111111111111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,19 +0,0 @@
|
||||
# Output products list for <hbdec2>
|
||||
hbdec2.asy
|
||||
hbdec2.gise
|
||||
hbdec2.mif
|
||||
hbdec2.ngc
|
||||
hbdec2.v
|
||||
hbdec2.veo
|
||||
hbdec2.xco
|
||||
hbdec2.xise
|
||||
hbdec2COEFF_auto0_0.mif
|
||||
hbdec2COEFF_auto0_1.mif
|
||||
hbdec2COEFF_auto0_2.mif
|
||||
hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
hbdec2_flist.txt
|
||||
hbdec2_readme.txt
|
||||
hbdec2_reload_addrfilt_decode_rom.mif
|
||||
hbdec2_reload_order.txt
|
||||
hbdec2_xmdf.tcl
|
||||
hbdec2filt_decode_rom.mif
|
||||
@@ -1,64 +0,0 @@
|
||||
The following files were generated for 'hbdec2' in directory
|
||||
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
|
||||
|
||||
Opens the IP Customization GUI:
|
||||
Allows the user to customize or recustomize the IP instance.
|
||||
|
||||
* hbdec2.mif
|
||||
* hbdec2_reload_order.txt
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* hbdec2.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* hbdec2.ngc
|
||||
* hbdec2.v
|
||||
* hbdec2.veo
|
||||
* hbdec2COEFF_auto0_0.mif
|
||||
* hbdec2COEFF_auto0_1.mif
|
||||
* hbdec2COEFF_auto0_2.mif
|
||||
* hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
* hbdec2_reload_addrfilt_decode_rom.mif
|
||||
* hbdec2filt_decode_rom.mif
|
||||
|
||||
Creates an HDL instantiation template:
|
||||
Creates an HDL instantiation template for the IP.
|
||||
|
||||
* hbdec2.veo
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* hbdec2.asy
|
||||
* hbdec2.mif
|
||||
* hbdec2_reload_order.txt
|
||||
|
||||
Generate ISE metadata:
|
||||
Create a metadata file for use when including this core in ISE designs
|
||||
|
||||
* hbdec2_xmdf.tcl
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* hbdec2.gise
|
||||
* hbdec2.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* hbdec2_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* hbdec2_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
000
|
||||
100
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
@@ -1,25 +0,0 @@
|
||||
Reload index 0 = Index 16
|
||||
Reload index 1 = Index 18
|
||||
Reload index 2 = Index 20
|
||||
Reload index 3 = Index 22
|
||||
Reload index 4 = Index 8
|
||||
Reload index 5 = Index 10
|
||||
Reload index 6 = Index 12
|
||||
Reload index 7 = Index 14
|
||||
Reload index 8 = Index 0
|
||||
Reload index 9 = Index 2
|
||||
Reload index 10 = Index 4
|
||||
Reload index 11 = Index 6
|
||||
Reload index 12 = Index 23
|
||||
Reload index 13 = Index 0
|
||||
Reload index 14 = Index 0
|
||||
Reload index 15 = Index 0
|
||||
Reload index 16 = Index 0
|
||||
Reload index 17 = Index 0
|
||||
Reload index 18 = Index 0
|
||||
Reload index 19 = Index 0
|
||||
Reload index 20 = Index 0
|
||||
Reload index 21 = Index 0
|
||||
Reload index 22 = Index 0
|
||||
Reload index 23 = Index 0
|
||||
|
||||
@@ -1,99 +0,0 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide hbdec2_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::hbdec2_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::hbdec2_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2
|
||||
}
|
||||
# ::hbdec2_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::hbdec2_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -1,17 +0,0 @@
|
||||
000
|
||||
100
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
000
|
||||
@@ -1,61 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 hbdec3
|
||||
RECTANGLE Normal 32 32 544 2048
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName nd
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din_1[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName din_2[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName coef_ld
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 880 32 880
|
||||
PIN 0 880 LEFT 36
|
||||
PINATTR PinName coef_we
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName coef_din[17:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1008 32 1008
|
||||
PIN 0 1008 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName ce
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1072 32 1072
|
||||
PIN 0 1072 LEFT 36
|
||||
PINATTR PinName sclr
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 240 544 240
|
||||
PIN 576 240 RIGHT 36
|
||||
PINATTR PinName dout_1[47:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 272 544 272
|
||||
PIN 576 272 RIGHT 36
|
||||
PINATTR PinName dout_2[47:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1840 544 1840
|
||||
PIN 576 1840 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1872 544 1872
|
||||
PIN 576 1872 RIGHT 36
|
||||
PINATTR PinName rdy
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1904 544 1904
|
||||
PIN 576 1904 RIGHT 36
|
||||
PINATTR PinName data_valid
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbdec3.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbdec3.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbdec3.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbdec3_reload_order.txt" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
@@ -1,63 +0,0 @@
|
||||
111111111111011101
|
||||
000000000000000000
|
||||
000000000001011111
|
||||
000000000000000000
|
||||
111111111100111101
|
||||
000000000000000000
|
||||
000000000101100000
|
||||
000000000000000000
|
||||
111111110110111010
|
||||
000000000000000000
|
||||
000000001110001011
|
||||
000000000000000000
|
||||
111111101010110110
|
||||
000000000000000000
|
||||
000000011110100001
|
||||
000000000000000000
|
||||
111111010101000001
|
||||
000000000000000000
|
||||
000000111011100101
|
||||
000000000000000000
|
||||
111110101101111111
|
||||
000000000000000000
|
||||
000001110001100000
|
||||
000000000000000000
|
||||
111101011111001000
|
||||
000000000000000000
|
||||
000011110010000110
|
||||
000000000000000000
|
||||
111001011000110101
|
||||
000000000000000000
|
||||
010100010011111100
|
||||
011111111111111111
|
||||
010100010011111100
|
||||
000000000000000000
|
||||
111001011000110101
|
||||
000000000000000000
|
||||
000011110010000110
|
||||
000000000000000000
|
||||
111101011111001000
|
||||
000000000000000000
|
||||
000001110001100000
|
||||
000000000000000000
|
||||
111110101101111111
|
||||
000000000000000000
|
||||
000000111011100101
|
||||
000000000000000000
|
||||
111111010101000001
|
||||
000000000000000000
|
||||
000000011110100001
|
||||
000000000000000000
|
||||
111111101010110110
|
||||
000000000000000000
|
||||
000000001110001011
|
||||
000000000000000000
|
||||
111111110110111010
|
||||
000000000000000000
|
||||
000000000101100000
|
||||
000000000000000000
|
||||
111111111100111101
|
||||
000000000000000000
|
||||
000000000001011111
|
||||
000000000000000000
|
||||
111111111111011101
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -1,79 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
|
||||
* *
|
||||
* This file contains confidential and proprietary information *
|
||||
* of Xilinx, Inc. and is protected under U.S. and *
|
||||
* international copyright and other intellectual property *
|
||||
* laws. *
|
||||
* *
|
||||
* DISCLAIMER *
|
||||
* This disclaimer is not a license and does not grant any *
|
||||
* rights to the materials distributed herewith. Except as *
|
||||
* otherwise provided in a valid license issued to you by *
|
||||
* Xilinx, and to the maximum extent permitted by applicable *
|
||||
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
||||
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
||||
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
||||
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
||||
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, *
|
||||
* including negligence, or under any other theory of *
|
||||
* liability) for any loss or damage of any kind or nature *
|
||||
* related to, arising under or in connection with these *
|
||||
* materials, including for any direct, or any indirect, *
|
||||
* special, incidental, or consequential loss or damage *
|
||||
* (including loss of data, profits, goodwill, or any type of *
|
||||
* loss or damage suffered as a result of any action brought *
|
||||
* by a third party) even if such damage or loss was *
|
||||
* reasonably foreseeable or Xilinx had been advised of the *
|
||||
* possibility of the same. *
|
||||
* *
|
||||
* CRITICAL APPLICATIONS *
|
||||
* Xilinx products are not designed or intended to be fail- *
|
||||
* safe, or for use in any application requiring fail-safe *
|
||||
* performance, such as life-support or safety devices or *
|
||||
* systems, Class III medical devices, nuclear facilities, *
|
||||
* applications related to the deployment of airbags, or any *
|
||||
* other applications that could lead to death, personal *
|
||||
* injury, or severe property or environmental damage *
|
||||
* (individually and collectively, "Critical *
|
||||
* Applications"). Customer assumes the sole risk and *
|
||||
* liability of any use of Xilinx products in Critical *
|
||||
* Applications, subject only to applicable laws and *
|
||||
* regulations governing limitations on product liability. *
|
||||
* *
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
||||
* PART OF THIS FILE AT ALL TIMES. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hbdec3 YourInstanceName (
|
||||
.sclr(sclr), // input sclr
|
||||
.clk(clk), // input clk
|
||||
.ce(ce), // input ce
|
||||
.nd(nd), // input nd
|
||||
.coef_ld(coef_ld), // input coef_ld
|
||||
.coef_we(coef_we), // input coef_we
|
||||
.coef_din(coef_din), // input [17 : 0] coef_din
|
||||
.rfd(rfd), // output rfd
|
||||
.rdy(rdy), // output rdy
|
||||
.data_valid(data_valid), // output data_valid
|
||||
.din_1(din_1), // input [23 : 0] din_1
|
||||
.din_2(din_2), // input [23 : 0] din_2
|
||||
.dout_1(dout_1), // output [47 : 0] dout_1
|
||||
.dout_2(dout_2)); // output [47 : 0] dout_2
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hbdec3.v when simulating
|
||||
// the core, hbdec3. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,102 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Wed Dec 4 21:31:43 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fir_compiler:5.0
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k325t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET allow_rounding_approximation=false
|
||||
CSET bestprecision=false
|
||||
CSET chan_in_adv=0
|
||||
CSET clock_frequency=200
|
||||
CSET coefficient_buffer_type=Automatic
|
||||
CSET coefficient_file=./hb63.coe
|
||||
CSET coefficient_fractional_bits=0
|
||||
CSET coefficient_reload=true
|
||||
CSET coefficient_sets=1
|
||||
CSET coefficient_sign=Signed
|
||||
CSET coefficient_structure=Half_Band
|
||||
CSET coefficient_width=18
|
||||
CSET coefficientsource=COE_File
|
||||
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
|
||||
CSET columnconfig=3
|
||||
CSET component_name=hbdec3
|
||||
CSET data_buffer_type=Automatic
|
||||
CSET data_fractional_bits=0
|
||||
CSET data_sign=Signed
|
||||
CSET data_width=24
|
||||
CSET decimation_rate=2
|
||||
CSET displayreloadorder=false
|
||||
CSET filter_architecture=Systolic_Multiply_Accumulate
|
||||
CSET filter_selection=1
|
||||
CSET filter_type=Decimation
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET hardwareoversamplingrate=1
|
||||
CSET has_ce=true
|
||||
CSET has_data_valid=true
|
||||
CSET has_nd=true
|
||||
CSET has_sclr=true
|
||||
CSET input_buffer_type=Automatic
|
||||
CSET inter_column_pipe_length=4
|
||||
CSET interpolation_rate=1
|
||||
CSET multi_column_support=Disabled
|
||||
CSET number_channels=1
|
||||
CSET number_paths=2
|
||||
CSET optimization_goal=Area
|
||||
CSET output_buffer_type=Automatic
|
||||
CSET output_rounding_mode=Full_Precision
|
||||
CSET output_width=48
|
||||
CSET passband_max=0.5
|
||||
CSET passband_min=0.0
|
||||
CSET preference_for_other_storage=Automatic
|
||||
CSET quantization=Integer_Coefficients
|
||||
CSET rate_change_type=Integer
|
||||
CSET ratespecification=Frequency_Specification
|
||||
CSET registered_output=true
|
||||
CSET sample_frequency=50
|
||||
CSET sampleperiod=1
|
||||
CSET sclr_deterministic=true
|
||||
CSET stopband_max=1.0
|
||||
CSET stopband_min=0.5
|
||||
CSET usechan_in_adv=false
|
||||
CSET zero_pack_factor=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T05:23:34Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 86e0fdc7
|
||||
@@ -1,72 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="hbdec3.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="hbdec3.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbdec3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="hbdec3.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbdec3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbdec3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-04T13:32:39" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0C4461115773DD979C3A5F377B8C29BF" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,17 +0,0 @@
|
||||
111111111111011101
|
||||
000000000001011111
|
||||
111111111100111101
|
||||
000000000101100000
|
||||
111111110110111010
|
||||
000000001110001011
|
||||
111111101010110110
|
||||
000000011110100001
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,17 +0,0 @@
|
||||
111111010101000001
|
||||
000000111011100101
|
||||
111110101101111111
|
||||
000001110001100000
|
||||
111101011111001000
|
||||
000011110010000110
|
||||
111001011000110101
|
||||
010100010011111100
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,3 +0,0 @@
|
||||
011111111111111111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,18 +0,0 @@
|
||||
# Output products list for <hbdec3>
|
||||
hbdec3.asy
|
||||
hbdec3.gise
|
||||
hbdec3.mif
|
||||
hbdec3.ngc
|
||||
hbdec3.v
|
||||
hbdec3.veo
|
||||
hbdec3.xco
|
||||
hbdec3.xise
|
||||
hbdec3COEFF_auto0_0.mif
|
||||
hbdec3COEFF_auto0_1.mif
|
||||
hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
hbdec3_flist.txt
|
||||
hbdec3_readme.txt
|
||||
hbdec3_reload_addrfilt_decode_rom.mif
|
||||
hbdec3_reload_order.txt
|
||||
hbdec3_xmdf.tcl
|
||||
hbdec3filt_decode_rom.mif
|
||||
@@ -1,63 +0,0 @@
|
||||
The following files were generated for 'hbdec3' in directory
|
||||
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
|
||||
|
||||
Opens the IP Customization GUI:
|
||||
Allows the user to customize or recustomize the IP instance.
|
||||
|
||||
* hbdec3.mif
|
||||
* hbdec3_reload_order.txt
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* hbdec3.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* hbdec3.ngc
|
||||
* hbdec3.v
|
||||
* hbdec3.veo
|
||||
* hbdec3COEFF_auto0_0.mif
|
||||
* hbdec3COEFF_auto0_1.mif
|
||||
* hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
* hbdec3_reload_addrfilt_decode_rom.mif
|
||||
* hbdec3filt_decode_rom.mif
|
||||
|
||||
Creates an HDL instantiation template:
|
||||
Creates an HDL instantiation template for the IP.
|
||||
|
||||
* hbdec3.veo
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* hbdec3.asy
|
||||
* hbdec3.mif
|
||||
* hbdec3_reload_order.txt
|
||||
|
||||
Generate ISE metadata:
|
||||
Create a metadata file for use when including this core in ISE designs
|
||||
|
||||
* hbdec3_xmdf.tcl
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* hbdec3.gise
|
||||
* hbdec3.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* hbdec3_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* hbdec3_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
0000
|
||||
1000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
@@ -1,33 +0,0 @@
|
||||
Reload index 0 = Index 16
|
||||
Reload index 1 = Index 18
|
||||
Reload index 2 = Index 20
|
||||
Reload index 3 = Index 22
|
||||
Reload index 4 = Index 24
|
||||
Reload index 5 = Index 26
|
||||
Reload index 6 = Index 28
|
||||
Reload index 7 = Index 30
|
||||
Reload index 8 = Index 0
|
||||
Reload index 9 = Index 2
|
||||
Reload index 10 = Index 4
|
||||
Reload index 11 = Index 6
|
||||
Reload index 12 = Index 8
|
||||
Reload index 13 = Index 10
|
||||
Reload index 14 = Index 12
|
||||
Reload index 15 = Index 14
|
||||
Reload index 16 = Index 31
|
||||
Reload index 17 = Index 0
|
||||
Reload index 18 = Index 0
|
||||
Reload index 19 = Index 0
|
||||
Reload index 20 = Index 0
|
||||
Reload index 21 = Index 0
|
||||
Reload index 22 = Index 0
|
||||
Reload index 23 = Index 0
|
||||
Reload index 24 = Index 0
|
||||
Reload index 25 = Index 0
|
||||
Reload index 26 = Index 0
|
||||
Reload index 27 = Index 0
|
||||
Reload index 28 = Index 0
|
||||
Reload index 29 = Index 0
|
||||
Reload index 30 = Index 0
|
||||
Reload index 31 = Index 0
|
||||
|
||||
@@ -1,95 +0,0 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide hbdec3_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::hbdec3_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::hbdec3_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec3
|
||||
}
|
||||
# ::hbdec3_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::hbdec3_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_1.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_addrfilt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_order.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3filt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec3
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -1,17 +0,0 @@
|
||||
0000
|
||||
1000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
@@ -1,61 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 hbint1
|
||||
RECTANGLE Normal 32 32 544 2048
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName nd
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din_1[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName din_2[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName coef_ld
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 880 32 880
|
||||
PIN 0 880 LEFT 36
|
||||
PINATTR PinName coef_we
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName coef_din[17:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1008 32 1008
|
||||
PIN 0 1008 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName ce
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1072 32 1072
|
||||
PIN 0 1072 LEFT 36
|
||||
PINATTR PinName sclr
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 240 544 240
|
||||
PIN 576 240 RIGHT 36
|
||||
PINATTR PinName dout_1[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 272 544 272
|
||||
PIN 576 272 RIGHT 36
|
||||
PINATTR PinName dout_2[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1840 544 1840
|
||||
PIN 576 1840 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1872 544 1872
|
||||
PIN 576 1872 RIGHT 36
|
||||
PINATTR PinName rdy
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1904 544 1904
|
||||
PIN 576 1904 RIGHT 36
|
||||
PINATTR PinName data_valid
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbint1.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbint1.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbint1.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbint1_reload_order.txt" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
@@ -1,63 +0,0 @@
|
||||
111111111111011101
|
||||
000000000000000000
|
||||
000000000001011111
|
||||
000000000000000000
|
||||
111111111100111101
|
||||
000000000000000000
|
||||
000000000101100000
|
||||
000000000000000000
|
||||
111111110110111010
|
||||
000000000000000000
|
||||
000000001110001011
|
||||
000000000000000000
|
||||
111111101010110110
|
||||
000000000000000000
|
||||
000000011110100001
|
||||
000000000000000000
|
||||
111111010101000001
|
||||
000000000000000000
|
||||
000000111011100101
|
||||
000000000000000000
|
||||
111110101101111111
|
||||
000000000000000000
|
||||
000001110001100000
|
||||
000000000000000000
|
||||
111101011111001000
|
||||
000000000000000000
|
||||
000011110010000110
|
||||
000000000000000000
|
||||
111001011000110101
|
||||
000000000000000000
|
||||
010100010011111100
|
||||
011111111111111111
|
||||
010100010011111100
|
||||
000000000000000000
|
||||
111001011000110101
|
||||
000000000000000000
|
||||
000011110010000110
|
||||
000000000000000000
|
||||
111101011111001000
|
||||
000000000000000000
|
||||
000001110001100000
|
||||
000000000000000000
|
||||
111110101101111111
|
||||
000000000000000000
|
||||
000000111011100101
|
||||
000000000000000000
|
||||
111111010101000001
|
||||
000000000000000000
|
||||
000000011110100001
|
||||
000000000000000000
|
||||
111111101010110110
|
||||
000000000000000000
|
||||
000000001110001011
|
||||
000000000000000000
|
||||
111111110110111010
|
||||
000000000000000000
|
||||
000000000101100000
|
||||
000000000000000000
|
||||
111111111100111101
|
||||
000000000000000000
|
||||
000000000001011111
|
||||
000000000000000000
|
||||
111111111111011101
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -1,79 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
|
||||
* *
|
||||
* This file contains confidential and proprietary information *
|
||||
* of Xilinx, Inc. and is protected under U.S. and *
|
||||
* international copyright and other intellectual property *
|
||||
* laws. *
|
||||
* *
|
||||
* DISCLAIMER *
|
||||
* This disclaimer is not a license and does not grant any *
|
||||
* rights to the materials distributed herewith. Except as *
|
||||
* otherwise provided in a valid license issued to you by *
|
||||
* Xilinx, and to the maximum extent permitted by applicable *
|
||||
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
||||
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
||||
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
||||
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
||||
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, *
|
||||
* including negligence, or under any other theory of *
|
||||
* liability) for any loss or damage of any kind or nature *
|
||||
* related to, arising under or in connection with these *
|
||||
* materials, including for any direct, or any indirect, *
|
||||
* special, incidental, or consequential loss or damage *
|
||||
* (including loss of data, profits, goodwill, or any type of *
|
||||
* loss or damage suffered as a result of any action brought *
|
||||
* by a third party) even if such damage or loss was *
|
||||
* reasonably foreseeable or Xilinx had been advised of the *
|
||||
* possibility of the same. *
|
||||
* *
|
||||
* CRITICAL APPLICATIONS *
|
||||
* Xilinx products are not designed or intended to be fail- *
|
||||
* safe, or for use in any application requiring fail-safe *
|
||||
* performance, such as life-support or safety devices or *
|
||||
* systems, Class III medical devices, nuclear facilities, *
|
||||
* applications related to the deployment of airbags, or any *
|
||||
* other applications that could lead to death, personal *
|
||||
* injury, or severe property or environmental damage *
|
||||
* (individually and collectively, "Critical *
|
||||
* Applications"). Customer assumes the sole risk and *
|
||||
* liability of any use of Xilinx products in Critical *
|
||||
* Applications, subject only to applicable laws and *
|
||||
* regulations governing limitations on product liability. *
|
||||
* *
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
||||
* PART OF THIS FILE AT ALL TIMES. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hbint1 YourInstanceName (
|
||||
.sclr(sclr), // input sclr
|
||||
.clk(clk), // input clk
|
||||
.ce(ce), // input ce
|
||||
.nd(nd), // input nd
|
||||
.coef_ld(coef_ld), // input coef_ld
|
||||
.coef_we(coef_we), // input coef_we
|
||||
.coef_din(coef_din), // input [17 : 0] coef_din
|
||||
.rfd(rfd), // output rfd
|
||||
.rdy(rdy), // output rdy
|
||||
.data_valid(data_valid), // output data_valid
|
||||
.din_1(din_1), // input [23 : 0] din_1
|
||||
.din_2(din_2), // input [23 : 0] din_2
|
||||
.dout_1(dout_1), // output [46 : 0] dout_1
|
||||
.dout_2(dout_2)); // output [46 : 0] dout_2
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hbint1.v when simulating
|
||||
// the core, hbint1. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,102 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Thu Dec 5 22:34:55 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fir_compiler:5.0
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k325t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET allow_rounding_approximation=false
|
||||
CSET bestprecision=false
|
||||
CSET chan_in_adv=0
|
||||
CSET clock_frequency=200
|
||||
CSET coefficient_buffer_type=Automatic
|
||||
CSET coefficient_file=./hb63.coe
|
||||
CSET coefficient_fractional_bits=0
|
||||
CSET coefficient_reload=true
|
||||
CSET coefficient_sets=1
|
||||
CSET coefficient_sign=Signed
|
||||
CSET coefficient_structure=Half_Band
|
||||
CSET coefficient_width=18
|
||||
CSET coefficientsource=COE_File
|
||||
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
|
||||
CSET columnconfig=3
|
||||
CSET component_name=hbint1
|
||||
CSET data_buffer_type=Automatic
|
||||
CSET data_fractional_bits=0
|
||||
CSET data_sign=Signed
|
||||
CSET data_width=24
|
||||
CSET decimation_rate=1
|
||||
CSET displayreloadorder=false
|
||||
CSET filter_architecture=Systolic_Multiply_Accumulate
|
||||
CSET filter_selection=1
|
||||
CSET filter_type=Interpolation
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET hardwareoversamplingrate=1
|
||||
CSET has_ce=true
|
||||
CSET has_data_valid=true
|
||||
CSET has_nd=true
|
||||
CSET has_sclr=true
|
||||
CSET input_buffer_type=Automatic
|
||||
CSET inter_column_pipe_length=4
|
||||
CSET interpolation_rate=2
|
||||
CSET multi_column_support=Disabled
|
||||
CSET number_channels=1
|
||||
CSET number_paths=2
|
||||
CSET optimization_goal=Area
|
||||
CSET output_buffer_type=Automatic
|
||||
CSET output_rounding_mode=Full_Precision
|
||||
CSET output_width=47
|
||||
CSET passband_max=0.43
|
||||
CSET passband_min=0.0
|
||||
CSET preference_for_other_storage=Automatic
|
||||
CSET quantization=Integer_Coefficients
|
||||
CSET rate_change_type=Integer
|
||||
CSET ratespecification=Frequency_Specification
|
||||
CSET registered_output=true
|
||||
CSET sample_frequency=25
|
||||
CSET sampleperiod=1
|
||||
CSET sclr_deterministic=true
|
||||
CSET stopband_max=1.0
|
||||
CSET stopband_min=0.57
|
||||
CSET usechan_in_adv=false
|
||||
CSET zero_pack_factor=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T05:23:34Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 4991bbb9
|
||||
@@ -1,72 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="hbint1.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="hbint1.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbint1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="hbint1.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbint1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbint1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-05T14:35:52" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9048954B661F64BB56A3564785FF4CAD" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,17 +0,0 @@
|
||||
111111111111011101
|
||||
000000000001011111
|
||||
111111111100111101
|
||||
000000000101100000
|
||||
111111110110111010
|
||||
000000001110001011
|
||||
111111101010110110
|
||||
000000011110100001
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,17 +0,0 @@
|
||||
111111010101000001
|
||||
000000111011100101
|
||||
111110101101111111
|
||||
000001110001100000
|
||||
111101011111001000
|
||||
000011110010000110
|
||||
111001011000110101
|
||||
010100010011111100
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,9 +0,0 @@
|
||||
111110111010101110
|
||||
000001110000011001
|
||||
111100110001111010
|
||||
001010001000000110
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,3 +0,0 @@
|
||||
011111111111111111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,18 +0,0 @@
|
||||
# Output products list for <hbint1>
|
||||
hbint1.asy
|
||||
hbint1.gise
|
||||
hbint1.mif
|
||||
hbint1.ngc
|
||||
hbint1.v
|
||||
hbint1.veo
|
||||
hbint1.xco
|
||||
hbint1.xise
|
||||
hbint1COEFF_auto0_0.mif
|
||||
hbint1COEFF_auto0_1.mif
|
||||
hbint1COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
hbint1_flist.txt
|
||||
hbint1_readme.txt
|
||||
hbint1_reload_addrfilt_decode_rom.mif
|
||||
hbint1_reload_order.txt
|
||||
hbint1_xmdf.tcl
|
||||
hbint1filt_decode_rom.mif
|
||||
@@ -1,63 +0,0 @@
|
||||
The following files were generated for 'hbint1' in directory
|
||||
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
|
||||
|
||||
Opens the IP Customization GUI:
|
||||
Allows the user to customize or recustomize the IP instance.
|
||||
|
||||
* hbint1.mif
|
||||
* hbint1_reload_order.txt
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* hbint1.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* hbint1.ngc
|
||||
* hbint1.v
|
||||
* hbint1.veo
|
||||
* hbint1COEFF_auto0_0.mif
|
||||
* hbint1COEFF_auto0_1.mif
|
||||
* hbint1COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
* hbint1_reload_addrfilt_decode_rom.mif
|
||||
* hbint1filt_decode_rom.mif
|
||||
|
||||
Creates an HDL instantiation template:
|
||||
Creates an HDL instantiation template for the IP.
|
||||
|
||||
* hbint1.veo
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* hbint1.asy
|
||||
* hbint1.mif
|
||||
* hbint1_reload_order.txt
|
||||
|
||||
Generate ISE metadata:
|
||||
Create a metadata file for use when including this core in ISE designs
|
||||
|
||||
* hbint1_xmdf.tcl
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* hbint1.gise
|
||||
* hbint1.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* hbint1_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* hbint1_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
0000
|
||||
1000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
@@ -1,33 +0,0 @@
|
||||
Reload index 0 = Index 16
|
||||
Reload index 1 = Index 18
|
||||
Reload index 2 = Index 20
|
||||
Reload index 3 = Index 22
|
||||
Reload index 4 = Index 24
|
||||
Reload index 5 = Index 26
|
||||
Reload index 6 = Index 28
|
||||
Reload index 7 = Index 30
|
||||
Reload index 8 = Index 0
|
||||
Reload index 9 = Index 2
|
||||
Reload index 10 = Index 4
|
||||
Reload index 11 = Index 6
|
||||
Reload index 12 = Index 8
|
||||
Reload index 13 = Index 10
|
||||
Reload index 14 = Index 12
|
||||
Reload index 15 = Index 14
|
||||
Reload index 16 = Index 31
|
||||
Reload index 17 = Index 0
|
||||
Reload index 18 = Index 0
|
||||
Reload index 19 = Index 0
|
||||
Reload index 20 = Index 0
|
||||
Reload index 21 = Index 0
|
||||
Reload index 22 = Index 0
|
||||
Reload index 23 = Index 0
|
||||
Reload index 24 = Index 0
|
||||
Reload index 25 = Index 0
|
||||
Reload index 26 = Index 0
|
||||
Reload index 27 = Index 0
|
||||
Reload index 28 = Index 0
|
||||
Reload index 29 = Index 0
|
||||
Reload index 30 = Index 0
|
||||
Reload index 31 = Index 0
|
||||
|
||||
@@ -1,95 +0,0 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide hbint1_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::hbint1_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::hbint1_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbint1
|
||||
}
|
||||
# ::hbint1_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::hbint1_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1COEFF_auto0_0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1COEFF_auto0_1.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1COEFF_auto_HALFBAND_CENTRE0.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1_reload_addrfilt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1_reload_order.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1filt_decode_rom.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbint1
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -1,17 +0,0 @@
|
||||
0000
|
||||
1000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
0000
|
||||
@@ -1,61 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 hbint2
|
||||
RECTANGLE Normal 32 32 544 2048
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName nd
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din_1[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName din_2[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName coef_ld
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 880 32 880
|
||||
PIN 0 880 LEFT 36
|
||||
PINATTR PinName coef_we
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName coef_din[17:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1008 32 1008
|
||||
PIN 0 1008 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName ce
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1072 32 1072
|
||||
PIN 0 1072 LEFT 36
|
||||
PINATTR PinName sclr
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 240 544 240
|
||||
PIN 576 240 RIGHT 36
|
||||
PINATTR PinName dout_1[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 272 544 272
|
||||
PIN 576 272 RIGHT 36
|
||||
PINATTR PinName dout_2[46:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1840 544 1840
|
||||
PIN 576 1840 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1872 544 1872
|
||||
PIN 576 1872 RIGHT 36
|
||||
PINATTR PinName rdy
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1904 544 1904
|
||||
PIN 576 1904 RIGHT 36
|
||||
PINATTR PinName data_valid
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbint2.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbint2.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbint2.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbint2_reload_order.txt" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
@@ -1,47 +0,0 @@
|
||||
111111111111000010
|
||||
000000000000000000
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
111111111001001000
|
||||
000000000000000000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
111111101000011111
|
||||
000000000000000000
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
111111000011000100
|
||||
000000000000000000
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
111101110000011101
|
||||
000000000000000000
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
111001100001011000
|
||||
000000000000000000
|
||||
010100010001000001
|
||||
011111111111111111
|
||||
010100010001000001
|
||||
000000000000000000
|
||||
111001100001011000
|
||||
000000000000000000
|
||||
000011100100101000
|
||||
000000000000000000
|
||||
111101110000011101
|
||||
000000000000000000
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
111111000011000100
|
||||
000000000000000000
|
||||
000000100110101110
|
||||
000000000000000000
|
||||
111111101000011111
|
||||
000000000000000000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
111111111001001000
|
||||
000000000000000000
|
||||
000000000011000010
|
||||
000000000000000000
|
||||
111111111111000010
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -1,79 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
|
||||
* *
|
||||
* This file contains confidential and proprietary information *
|
||||
* of Xilinx, Inc. and is protected under U.S. and *
|
||||
* international copyright and other intellectual property *
|
||||
* laws. *
|
||||
* *
|
||||
* DISCLAIMER *
|
||||
* This disclaimer is not a license and does not grant any *
|
||||
* rights to the materials distributed herewith. Except as *
|
||||
* otherwise provided in a valid license issued to you by *
|
||||
* Xilinx, and to the maximum extent permitted by applicable *
|
||||
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
||||
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
||||
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
||||
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
||||
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
||||
* (2) Xilinx shall not be liable (whether in contract or tort, *
|
||||
* including negligence, or under any other theory of *
|
||||
* liability) for any loss or damage of any kind or nature *
|
||||
* related to, arising under or in connection with these *
|
||||
* materials, including for any direct, or any indirect, *
|
||||
* special, incidental, or consequential loss or damage *
|
||||
* (including loss of data, profits, goodwill, or any type of *
|
||||
* loss or damage suffered as a result of any action brought *
|
||||
* by a third party) even if such damage or loss was *
|
||||
* reasonably foreseeable or Xilinx had been advised of the *
|
||||
* possibility of the same. *
|
||||
* *
|
||||
* CRITICAL APPLICATIONS *
|
||||
* Xilinx products are not designed or intended to be fail- *
|
||||
* safe, or for use in any application requiring fail-safe *
|
||||
* performance, such as life-support or safety devices or *
|
||||
* systems, Class III medical devices, nuclear facilities, *
|
||||
* applications related to the deployment of airbags, or any *
|
||||
* other applications that could lead to death, personal *
|
||||
* injury, or severe property or environmental damage *
|
||||
* (individually and collectively, "Critical *
|
||||
* Applications"). Customer assumes the sole risk and *
|
||||
* liability of any use of Xilinx products in Critical *
|
||||
* Applications, subject only to applicable laws and *
|
||||
* regulations governing limitations on product liability. *
|
||||
* *
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
||||
* PART OF THIS FILE AT ALL TIMES. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hbint2 YourInstanceName (
|
||||
.sclr(sclr), // input sclr
|
||||
.clk(clk), // input clk
|
||||
.ce(ce), // input ce
|
||||
.nd(nd), // input nd
|
||||
.coef_ld(coef_ld), // input coef_ld
|
||||
.coef_we(coef_we), // input coef_we
|
||||
.coef_din(coef_din), // input [17 : 0] coef_din
|
||||
.rfd(rfd), // output rfd
|
||||
.rdy(rdy), // output rdy
|
||||
.data_valid(data_valid), // output data_valid
|
||||
.din_1(din_1), // input [23 : 0] din_1
|
||||
.din_2(din_2), // input [23 : 0] din_2
|
||||
.dout_1(dout_1), // output [46 : 0] dout_1
|
||||
.dout_2(dout_2)); // output [46 : 0] dout_2
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hbint2.v when simulating
|
||||
// the core, hbint2. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,102 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Fri Dec 6 01:34:46 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fir_compiler:5.0
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k325t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET allow_rounding_approximation=false
|
||||
CSET bestprecision=false
|
||||
CSET chan_in_adv=0
|
||||
CSET clock_frequency=200
|
||||
CSET coefficient_buffer_type=Automatic
|
||||
CSET coefficient_file=./hb47.coe
|
||||
CSET coefficient_fractional_bits=0
|
||||
CSET coefficient_reload=true
|
||||
CSET coefficient_sets=1
|
||||
CSET coefficient_sign=Signed
|
||||
CSET coefficient_structure=Half_Band
|
||||
CSET coefficient_width=18
|
||||
CSET coefficientsource=COE_File
|
||||
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
|
||||
CSET columnconfig=4
|
||||
CSET component_name=hbint2
|
||||
CSET data_buffer_type=Automatic
|
||||
CSET data_fractional_bits=0
|
||||
CSET data_sign=Signed
|
||||
CSET data_width=24
|
||||
CSET decimation_rate=1
|
||||
CSET displayreloadorder=false
|
||||
CSET filter_architecture=Systolic_Multiply_Accumulate
|
||||
CSET filter_selection=1
|
||||
CSET filter_type=Interpolation
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET hardwareoversamplingrate=1
|
||||
CSET has_ce=true
|
||||
CSET has_data_valid=true
|
||||
CSET has_nd=true
|
||||
CSET has_sclr=true
|
||||
CSET input_buffer_type=Automatic
|
||||
CSET inter_column_pipe_length=4
|
||||
CSET interpolation_rate=2
|
||||
CSET multi_column_support=Disabled
|
||||
CSET number_channels=1
|
||||
CSET number_paths=2
|
||||
CSET optimization_goal=Area
|
||||
CSET output_buffer_type=Automatic
|
||||
CSET output_rounding_mode=Full_Precision
|
||||
CSET output_width=47
|
||||
CSET passband_max=0.41
|
||||
CSET passband_min=0.0
|
||||
CSET preference_for_other_storage=Automatic
|
||||
CSET quantization=Integer_Coefficients
|
||||
CSET rate_change_type=Integer
|
||||
CSET ratespecification=Frequency_Specification
|
||||
CSET registered_output=true
|
||||
CSET sample_frequency=50
|
||||
CSET sampleperiod=1
|
||||
CSET sclr_deterministic=true
|
||||
CSET stopband_max=1.0
|
||||
CSET stopband_min=0.59
|
||||
CSET usechan_in_adv=false
|
||||
CSET zero_pack_factor=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T05:23:34Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: a3f01bd
|
||||
@@ -1,72 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="hbint2.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="hbint2.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbint2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="hbint2.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbint2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbint2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-05T17:35:41" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D8426CFC4E2E1B6F70716358AFC4E1A1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,9 +0,0 @@
|
||||
111111111111000010
|
||||
000000000011000010
|
||||
111111111001001000
|
||||
000000001101010111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,9 +0,0 @@
|
||||
111111101000011111
|
||||
000000100110101110
|
||||
111111000011000100
|
||||
000001011101100110
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,9 +0,0 @@
|
||||
111101110000011101
|
||||
000011100100101000
|
||||
111001100001011000
|
||||
010100010001000001
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
@@ -1,3 +0,0 @@
|
||||
011111111111111111
|
||||
000000000000000000
|
||||
000000000000000000
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user