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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun committed 2014-10-07 11:25:20 +02:00
1 parent 56e84828fe
commit 74893643ca
2415 files changed
-1492030
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top/x300/coregen_dsp/.gitignore
-4
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@@ -1,4 +0,0 @@
_xmsgs
*.log
*.ncf
top/x300/coregen_dsp/.lso
-1
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@@ -1 +0,0 @@
fir_compiler_v5_0
top/x300/coregen_dsp/Makefile.srcs
-23
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@@ -1,23 +0,0 @@
#
# Copyright 2012 Ettus Research LLC
#
##################################################
# Coregen Sources
##################################################
COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x300/coregen_dsp/, \
hbdec1.v \
hbdec1.xco \
hbdec2.v \
hbdec2.xco \
hbdec3.v \
hbdec3.xco \
hbint1.v \
hbint1.xco \
hbint2.v \
hbint2.xco \
hbint3.v \
hbint3.xco \
))
top/x300/coregen_dsp/coregen.cgp
-9
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@@ -1,9 +0,0 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Other
SET package = ffg900
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
top/x300/coregen_dsp/filt2.coe
-36
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@@ -1,36 +0,0 @@
Radix=10;
CoefData = 282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282;
top/x300/coregen_dsp/hb31.coe
-32
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@@ -1,32 +0,0 @@
Radix=10;
CoefData = -581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581;
top/x300/coregen_dsp/hb35.coe
-36
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@@ -1,36 +0,0 @@
Radix=10;
CoefData = 282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282;
top/x300/coregen_dsp/hb39.coe
-40
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@@ -1,40 +0,0 @@
Radix=10;
CoefData = -102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102;
top/x300/coregen_dsp/hb43.coe
-44
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@@ -1,44 +0,0 @@
Radix=10;
CoefData = 100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100;
top/x300/coregen_dsp/hb47.coe
-51
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@@ -1,51 +0,0 @@
; Generated with round((2^18-2)*halfgen_test(.21,12,1))
; 83% effective BW, 64dB to 85dB rolloff
Radix=10;
CoefData =
-62,
0,
194,
0,
-440,
0,
855,
0,
-1505,
0,
2478,
0,
-3900,
0,
5990,
0,
-9187,
0,
14632,
0,
-26536,
0,
83009,
131071,
83009,
0,
-26536,
0,
14632,
0,
-9187,
0,
5990,
0,
-3900,
0,
2478,
0,
-1505,
0,
855,
0,
-440,
0
194,
0,
-62;
top/x300/coregen_dsp/hb51.coe
-52
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@@ -1,52 +0,0 @@
Radix=10;
CoefData = 300,
0,
-200,
0,
100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100,
0,
-200,
0,
300;
top/x300/coregen_dsp/hb55.coe
-56
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@@ -1,56 +0,0 @@
Radix=10;
CoefData = -400,
0,
300,
0,
-200,
0,
100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100,
0,
-200,
0,
300,
0,
-400;
top/x300/coregen_dsp/hb59.coe
-60
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@@ -1,60 +0,0 @@
Radix=10;
CoefData = 500,
0,
-400,
0,
300,
0,
-200,
0,
100,
0,
-102,
0,
282,
-0,
-581,
0,
1053,
-0,
-1759,
0,
2814,
-0,
-4434,
0,
7193,
-0,
-13190,
0,
41478,
65536,
41478,
0,
-13190,
-0,
7193,
0,
-4434,
-0,
2814,
0,
-1759,
-0,
1053,
0,
-581,
-0,
282,
0,
-102,
0,
100,
0,
-200,
0,
300,
0,
-400,
0
500;
top/x300/coregen_dsp/hb63.coe
-67
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@@ -1,67 +0,0 @@
; Generated with round((2^18-2)*halfgen_test(.22,16,1))
; 88% effective BW, 64dB to 87dB rolloff
Radix=10;
CoefData =
-35,
0,
95,
0,
-195,
0,
352,
0,
-582,
0,
907,
0,
-1354,
0,
1953,
0,
-2751,
0,
3813,
0,
-5249,
0,
7264,
0,
-10296,
0,
15494,
0,
-27083,
0,
83196,
131071,
83196,
0,
-27083,
0,
15494,
0,
-10296,
0,
7264,
0,
-5249,
0,
3813,
0,
-2751,
0,
1953,
0,
-1354,
0,
907,
0,
-582,
0,
352,
0,
-195,
0
95,
0
-35;
top/x300/coregen_dsp/hbdec1.asy
-61
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@@ -1,61 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbdec1
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[46:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[46:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbdec1.gise
-32
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@@ -1,32 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbdec1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbdec1.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbdec1.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbdec1_reload_order.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_dsp/hbdec1.mif
-47
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@@ -1,47 +0,0 @@
111111111111000010
000000000000000000
000000000011000010
000000000000000000
111111111001001000
000000000000000000
000000001101010111
000000000000000000
111111101000011111
000000000000000000
000000100110101110
000000000000000000
111111000011000100
000000000000000000
000001011101100110
000000000000000000
111101110000011101
000000000000000000
000011100100101000
000000000000000000
111001100001011000
000000000000000000
010100010001000001
011111111111111111
010100010001000001
000000000000000000
111001100001011000
000000000000000000
000011100100101000
000000000000000000
111101110000011101
000000000000000000
000001011101100110
000000000000000000
111111000011000100
000000000000000000
000000100110101110
000000000000000000
111111101000011111
000000000000000000
000000001101010111
000000000000000000
111111111001001000
000000000000000000
000000000011000010
000000000000000000
111111111111000010
top/x300/coregen_dsp/hbdec1.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$22g6~753-Xnzd}foo8#5+421).97 ?>;168456702:;<=>?01a8456789:;<=>?8:2345678820<=>?0121<>6789:;<>6401236567:2:?>6>61:30?4(7:2;;86??0133?4>=AGZ^X7L31683:45<910BB][[:CAJJ970294:86?7:HLSQQ<CIVCE0<950?34?4>=AGZ^X7m`eg]gmk:6?3:5=85>8;MVPUSS2KIDYY2>7;2=53=603E^X][[:EC\KPR;9>0;2<84198LQQVR\3NISB[[<0594;76380BB][[:@FGV96=87;97<4FNQWW>DBCZH6;6=0>2:39MKVR\3KOH_L30;2=5f=62@D[YY4lodd\bljsm{Uxia2?:1<23>7=AGZ^X7hflugq[vck490;2<;41;MVPUSS2jbjbRga<183:40<93E^X][[:bjbjZir|5:1<3?423914==58HK9<?>>6:07>LHW]]0OMYOPIO>17?699;1987GAPTV9`lh;::0;2<;4258JJUSS2mceS<>32283:43<:=0BB][[:ekm[47;::0;2<;4258JJUSS2mceS<<32283:43<:=0BB][[:ekm[45;::0;2<;4258JJUSS2mceS<:32283:43<:=0BB][[:ekm[43;::0;2<;4258JJUSS2mceS<832283:42<:=0BB][[:ekm[4:5;3:5=95=4;KMTPR=l`dT>1<<:1<20>432@D[YY4kio]0875=87;?7?:5IORVP?bnfV>7>>4?>06861<NFY__6iga_4>17?699=1987GAPTV9`lhX>5886=0>4:07>LHW]]0oecQ8<3194;733;>1EC^ZT;fjjZ>;::0;2<:4258JJUSS2mceS42=3;2=5==5<3E^X][[:ECWEZIR\5886=0>6:07>JSSX\^1hb{{_h>17?69901987AZTQWW>air|VcT==2=3;2=5<=5<3E^X][[:emvpZoX9869?7>118910?IR\Y__6iazt^k\57:5;3:5=45=4;MVPUSS2me~xRgP12>17?69901987AZTQWW>air|VcT=92=3;2=5<=5<3E^X][[:emvpZoX9<69?7>118910?IR\Y__6iazt^k\53:5;3:5=55=4;MVPUSS2me~xRgP1=00>586028?6B[[PTV9`jssW`U90?=50?3;?72=G\^[YY4kotv\mZ5;::0;2<64258LQQVR\3ndyyQf_5>17?69911987AZTQWW>air|VcT91<<:1<2<>432F__\XZ5dnww[lY14;91<3?7;369KPRW]]0ocxzPi^5?66<76820>94@UURVP?bh}}UbS52=3;2=5==5<3E^X][[:emvpZoX15886=0>0:06>LHW]]0O0?:50?31?7<NFY__6LJKR@>2>586:281EC^ZT;CG@WD;93:5==5<0;KMTPR=I5826=0>3:13>LHW]]0JOD@32883:43<;90DYY^ZT;C@KPR;:00;2<<43;KMTPR=IMNYM1<50?31?6<NFY__6LJKRC>1>586?291EC^ZT;ABVW_NFZOG0?4?>06802<H]]Z^X7j`uu>72?699>1?;7AZTQWW>air|V;;09850?34?11=G\^[YY4kotv\54:3>3:5=:5;7;MVPUSS2me~xR?=<5494;703==1CXZ_UU8gkprX9:6?:7>116973?IR\Y__6iazt^37810=87;<7995OTVSQQ<cg|~T=82;6;2=52=3?3E^X][[:emvpZ714=<1<3?9;559KPRW]]0ocxzP1=65>586>2><6B[[PTV9`jssW;6?:7>117973?IR\Y__6iazt^1?03<768<08:4@UURVP?bh}}U?09850?35?11=G\^[YY4kotv\1921294::6:8:NWWTPR=lfS;2;6;2=53=3?3E^X][[:emvpZ1;<?0;2<84468LQQVR\3ndyyQ7<5494;713==1CXZ_UU8gkprX15>=6=0>6:64>JSSX\^1hb{{_p>72?69901?;7AZTQWW>air|V{T==2;6;2=5<=3?3E^X][[:emvpZwX986?:7>118973?IR\Y__6iazt^s\57:3>3:5=45;7;MVPUSS2me~xRP12>72?69901?;7AZTQWW>air|V{T=92;6;2=5<=3?3E^X][[:emvpZwX9<6?:7>118973?IR\Y__6iazt^s\53:3>3:5=55;7;MVPUSS2me~xRP1=65>58602><6B[[PTV9`jssWxU909850?3;?11=G\^[YY4kotv\uZ5;<?0;2<64468LQQVR\3ndyyQ~_5>72?69911?;7AZTQWW>air|V{T91:9:1<2<>202F__\XZ5dnww[tY14=<1<3?7;559KPRW]]0ocxzPq^5?03<768208:4@UURVP?bh}}UzS52;6;2=5==3?3E^X][[:emvpZwX15>=6=0>0:6;>LHW]]0H09950?37?1>=AGZ^X7JN_HL?02<76890854FNQWW>UENF5><6=0>6:6;>JSSX\^1HLQ@UU>73?699?1?47AZTQWW>ADXG\^78:4?>0380=<H]]Z^X7^34683:43<<10DYY^ZT;R@KPR;<>0;2<:44;KMTPR=IE_FCIK33;2=53=32F__\XZ5C@PQ]JSS4:0;255;F56701233<;?<95:55227>3=AGZ^X7GAMNFF81<7681=868NA@:82DGFIHKJ>68L1:51?246;2=1EC^ZT;MSIJBB4?0;2?58Fd94o642|oll5=>"209;0>>?81805L<4A108E44<I;80M><4A568E969=2K7==0:;@>25;3<I5;9285N<01=1>G;9=4>7L2>5?78E9716<1J0<915:C?5=823H6:53:4A=3=1>G;:94>7L2=1?78E9456<1J0?=15:C?61823H6993;4A=05:0=F4;=596O329<4?D:513:596O328<7?D:56=1J0>0;;@>7:1=F4<4?7L29>59B82833H63295N<8<;?DEF[JXNK:5NCHL?4;><IJCE0<>18:C@MK:69720MNGA<00=<>GDAG6:?364ABKM842902KHEC2>5?:8EFOI48<546OLIO>23;><IJCE0<618:C@MK:617=0MNGA<0<;?DENF58;255NCHL?648?3HIBB1<=>99BGLH;::437LMFN=07:==FK@D7>807;@AJJ941611JOD@326<;?DENF5832l5NCHL?6<<7611JOD@328<4?DENF585;6OLIO>0:2=FK@D78394ABKM80803HIBB1817:C@MK:06>1JOD@38?58EFOI40437LM@UU>3:<=FKF__0<>19:C@KPR;98427LM@UU>26;?<IJE^X1?<>89BGJSS48>556OLOTV?508>3HIDYY2>6?;8EFIR\5;<245NCNWW84>912KHCXZ318<;?DEH]]6:245NCNWW876912KHCXZ320<:?DEH]]69>374ABMVP944601JOB[[<36==>GDG\^7>806;@ALQQ:5>730MNAZT=04:<=FKF__0?61b:C@KPR;:00;245NCNWW87?902KHCXZ32?:8EFIR\59546OLOTV?0;><IJE^X1;18:C@KPR;>720MNAZT=5=<>GDG\^74364ABMVP9?912KOH_2?:1<4?DBCZ5:5m6OKDSC?4?6902KOH_O30?c8EABUI5;1<364AEFQE979i2KOH_O32;2=<>GCL[K7>3o4AEFQF96=8720MIJ]B=2=e>GCL[H7=7>18:CG@WD;97k0MIJ]B=094;><IMNYN1<15:CGV@Af3HF^ABJJ<1<b?DJREFNN0<0n;@NVIJBB4;4h7LBZMNFF86<76h1J@XC@DD>0:d=FD\GDHH\JG59BV@A682K^XB\JSDV\TDRCM]=0MRGAPTV7?G:76<1I0<>15:@?54823K6:>3;4B=30:0=E48>596L314<6?G:6>7=0N1?8:1<6?G:6?7>0N1?14:@?6;2<J59586L34?68F939<2H7:3:4B=5=0>D;07>0N1718:@@EVEUMN=0NNGA<1<;?GENF5;;255MCHL?548?3KIBB1?=>99AGLH;9:437OMFN=37:==EK@D7=807;CAJJ9716h1IOD@31683:==EK@D7=:08;CAJJ979?2HHEC2=>69AGLH;;7=0NNGA<5<4?GENF5?5;6LLIO>5:2=EK@D7;394BBKM8=803KIBB1718:@@KPR;8730NNAZT=33:<=EKF__0<?19:@@KPR;9;427OM@UU>27;?<JJE^X1?;>89AGJSS48?556LLOTV?538e3KIDYY2>7;2==>DDG\^7=:07;CALQQ:6611IOB[[<3<;?GEH]]68255MCNWW818?3KIDYY2:>99AGJSS4?437OM@UU>4:==EKF__0507;CALQQ:>6=1I^HI7;CWP[LHAG>1ISD@_UU38G1=D494>7N2>0?78G9766<1H0<<15:A?56823J6:83;4C=36:0=D48<596M316<6?F:607?0O1?6>59@84823J69<3;4C=02:0=D4;8596M322<6?F:5<7?0O1<:>49@8709=2I7>:0:;B>1<;3<K582295L<3<6?F:487?0O1=>>49@8649=2I7?>0:;B>00;3<K59>285L<24=1>E;;>4>7N2<8?78G95>6=1H0>0:;B>74;3<K5>:285L<50=1>E;<:4>7N2;4?78G9226<1H09817:A?02<76<1H09914:A?0;2<K5?586M36?68G919<2I743:4C=;=f>EFZ[SHM^MFNb9@EWT^KHYHCXZ8;BCQV\OIi2IJ^_WFNSGD`>EFZ[SBB^KC<1<g?FGUZPCE_HB31?d8GDTUQ@DXIA2=:1<g?FGUZPCE_HB32?f8GDTUQ@DXIA\JGc9@EWT^G\^7<3l4C@PQ]JSS484i7NO]RXMVP94Line truncated
top/x300/coregen_dsp/hbdec1.v
-39998
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top/x300/coregen_dsp/hbdec1.veo
-79
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/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec1 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec1.v when simulating
// the core, hbdec1. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbdec1.xco
-102
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@@ -1,102 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Dec 4 21:34:29 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200.0
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb47.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=7
CSET component_name=hbdec1
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=200
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: 8b63d7c7
top/x300/coregen_dsp/hbdec1.xise
-72
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="hbdec1.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="hbdec1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbdec1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="hbdec1.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbdec1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbdec1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-04T13:35:30" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A940ACE469CBDB14A68CA6C88B3234B8" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_dsp/hbdec1COEFF_auto0_0.mif
-5
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@@ -1,5 +0,0 @@
111111111111000010
000000000011000010
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_1.mif
-5
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@@ -1,5 +0,0 @@
111111111001001000
000000001101010111
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_2.mif
-5
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@@ -1,5 +0,0 @@
111111101000011111
000000100110101110
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_3.mif
-5
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@@ -1,5 +0,0 @@
111111000011000100
000001011101100110
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_4.mif
-5
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@@ -1,5 +0,0 @@
111101110000011101
000011100100101000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto0_5.mif
-5
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@@ -1,5 +0,0 @@
111001100001011000
010100010001000001
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
-3
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@@ -1,3 +0,0 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec1_flist.txt
-22
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@@ -1,22 +0,0 @@
# Output products list for <hbdec1>
hbdec1.asy
hbdec1.gise
hbdec1.mif
hbdec1.ngc
hbdec1.v
hbdec1.veo
hbdec1.xco
hbdec1.xise
hbdec1COEFF_auto0_0.mif
hbdec1COEFF_auto0_1.mif
hbdec1COEFF_auto0_2.mif
hbdec1COEFF_auto0_3.mif
hbdec1COEFF_auto0_4.mif
hbdec1COEFF_auto0_5.mif
hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
hbdec1_flist.txt
hbdec1_readme.txt
hbdec1_reload_addrfilt_decode_rom.mif
hbdec1_reload_order.txt
hbdec1_xmdf.tcl
hbdec1filt_decode_rom.mif
top/x300/coregen_dsp/hbdec1_readme.txt
-67
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@@ -1,67 +0,0 @@
The following files were generated for 'hbdec1' in directory
/home/matt/fpgadev/usrp3/top/x300/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbdec1.mif
* hbdec1_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbdec1.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbdec1.ngc
* hbdec1.v
* hbdec1.veo
* hbdec1COEFF_auto0_0.mif
* hbdec1COEFF_auto0_1.mif
* hbdec1COEFF_auto0_2.mif
* hbdec1COEFF_auto0_3.mif
* hbdec1COEFF_auto0_4.mif
* hbdec1COEFF_auto0_5.mif
* hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
* hbdec1_reload_addrfilt_decode_rom.mif
* hbdec1filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbdec1.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbdec1.asy
* hbdec1.mif
* hbdec1_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbdec1_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbdec1.gise
* hbdec1.xise
Deliver Readme:
Readme file for the IP.
* hbdec1_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbdec1_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif
-17
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00
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
top/x300/coregen_dsp/hbdec1_reload_order.txt
-25
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@@ -1,25 +0,0 @@
Reload index 0 = Index 20
Reload index 1 = Index 22
Reload index 2 = Index 16
Reload index 3 = Index 18
Reload index 4 = Index 12
Reload index 5 = Index 14
Reload index 6 = Index 8
Reload index 7 = Index 10
Reload index 8 = Index 4
Reload index 9 = Index 6
Reload index 10 = Index 0
Reload index 11 = Index 2
Reload index 12 = Index 23
Reload index 13 = Index 0
Reload index 14 = Index 0
Reload index 15 = Index 0
Reload index 16 = Index 0
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
top/x300/coregen_dsp/hbdec1_xmdf.tcl
-111
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@@ -1,111 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide hbdec1_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbdec1_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbdec1_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1
}
# ::hbdec1_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbdec1_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbdec1filt_decode_rom.mif
-17
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00
10
00
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00
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00
00
00
00
00
00
00
00
00
00
00
top/x300/coregen_dsp/hbdec2.asy
-61
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@@ -1,61 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbdec2
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[46:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[46:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbdec2.gise
-32
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@@ -1,32 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbdec2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbdec2.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbdec2.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbdec2_reload_order.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_dsp/hbdec2.mif
-47
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@@ -1,47 +0,0 @@
111111111111000010
000000000000000000
000000000011000010
000000000000000000
111111111001001000
000000000000000000
000000001101010111
000000000000000000
111111101000011111
000000000000000000
000000100110101110
000000000000000000
111111000011000100
000000000000000000
000001011101100110
000000000000000000
111101110000011101
000000000000000000
000011100100101000
000000000000000000
111001100001011000
000000000000000000
010100010001000001
011111111111111111
010100010001000001
000000000000000000
111001100001011000
000000000000000000
000011100100101000
000000000000000000
111101110000011101
000000000000000000
000001011101100110
000000000000000000
111111000011000100
000000000000000000
000000100110101110
000000000000000000
111111101000011111
000000000000000000
000000001101010111
000000000000000000
111111111001001000
000000000000000000
000000000011000010
000000000000000000
111111111111000010
top/x300/coregen_dsp/hbdec2.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$3155~753-Xnzd}foo8#5+421).97 ?>;168456702:;<=>?01a8456789:;<=>?8:2345678820<=>?0121<>6789:;<>640123456302:;<=>?04:8456789:=46>?012342><89:;<=>78:2345678020<=>?012B<>6789:;<O640123456D02:;<=>?0E:8456789:M46>?0103454<8=80<4?41292*54<99>0==>?1192<?OIX\^1N1?8:1<27>7?2@D[YY4MCHL?52<768>0=54FNQWW>AGXAG6:;7>11692<?OIX\^1obki_ekm841=87;>7<65OTVSQQ<EKF__0<950?35?4>=G\^[YY4KA^MVP970294::6?7:NWWTPR=LKUDYY2>7;2=57=62@D[YY4NDEPB85<76880=7GAPTV9EABUJ5:1<3?l;08JJUSS2jenjRhflugq[vck490;2<941;KMTPR=n`fiQ|em>3>586=2;1CXZ_UU8`ldhXag6;6=0>6:39KPRW]]0hdl`Potv?4?6992837?>NA321440<:=0BB][[:ECWEZOI4;91<3?=;369MKVR\3nbb1<<:1<21>432@D[YY4kio]24944294:96<;:HLSQQ<cagU:=1<<:1<21>432@D[YY4kio]26944294:96<;:HLSQQ<cagU:?1<<:1<21>432@D[YY4kio]20944294:96<;:HLSQQ<cagU:91<<:1<21>432@D[YY4kio]22944294:86<;:HLSQQ<cagU:0?=50?37?72=AGZ^X7jfn^0?66<768>0>94FNQWW>aoiW:69?7>115910?OIX\^1hd`P4=00>586<28?6D@_UU8gmkY24;91<3?;;369MKVR\3nbbR832283:42<:=0BB][[:ekm[2:5;3:5=95=4;KMTPR=l`dT41<<:1<20>432@D[YY4kio]:875=87;37?:5OTVSQQ<CI]KTCXZ32283:40<:=0DYY^ZT;flqqYn4;91<3?6;369KPRW]]0ocxzPi^33875=87;27?:5OTVSQQ<cg|~TeR?><3194;7>3;>1CXZ_UU8gkprXaV;90?=50?3:?72=G\^[YY4kotv\mZ744;91<3?6;369KPRW]]0ocxzPi^37875=87;27?:5OTVSQQ<cg|~TeR?:<3194;7>3;>1CXZ_UU8gkprXaV;=0?=50?3;?72=G\^[YY4kotv\mZ7;::0;2<64258LQQVR\3ndyyQf_3>17?69911987AZTQWW>air|VcT?1<<:1<2<>432F__\XZ5dnww[lY34;91<3?7;369KPRW]]0ocxzPi^7?66<76820>94@UURVP?bh}}UbS;2=3;2=5==5<3E^X][[:emvpZoX?5886=0>8:07>JSSX\^1hb{{_h];875=87;37?:5OTVSQQ<cg|~TeR732283:46<:<0BB][[:E>10?6998196D@_UU8B@AT;93:5=?5=:HLSQQ<FLMXJ0<4?>0086?OIX\^1MIJ]B=394;773::1EC^ZT;C?6<<76890?=4FNQWW>DENF5826=0>5:13>JSSX\^1MNAZT=0:>586:291EC^ZT;CG@WG;:3:5=?5<:HLSQQ<FLMXI0?4?>0587?OIX\^1OL\]YHLPAI:5294979>>4:64>JSSX\^1hb{{<5494;703==1CXZ_UU8gkprX996?:7>116973?IR\Y__6iazt^32810=87;<7995OTVSQQ<cg|~T=?2;6;2=52=3?3E^X][[:emvpZ744=<1<3?8;559KPRW]]0ocxzP15>72?699>1?;7AZTQWW>air|V;>09850?34?11=G\^[YY4kotv\53:3>3:5=;5;7;MVPUSS2me~xR?34783:40<<>0DYY^ZT;flqqY54=<1<3?9;559KPRW]]0ocxzP3=65>586>2><6B[[PTV9`jssW=6?:7>117973?IR\Y__6iazt^7?03<768<08:4@UURVP?bh}}U=09850?35?11=G\^[YY4kotv\3921294::6:8:NWWTPR=lfS52;6;2=53=3?3E^X][[:emvpZ?;<?0;2<84468LQQVR\3ndyyQ~<5494;7>3==1CXZ_UU8gkprXyV;;09850?3:?11=G\^[YY4kotv\uZ764=<1<3?6;559KPRW]]0ocxzPq^31810=87;27995OTVSQQ<cg|~T}R?<<5494;7>3==1CXZ_UU8gkprXyV;?09850?3:?11=G\^[YY4kotv\uZ724=<1<3?6;559KPRW]]0ocxzPq^35810=87;37995OTVSQQ<cg|~T}R?34783:4><<>0DYY^ZT;flqqYvW;6?:7>119973?IR\Y__6iazt^s\7921294:46:8:NWWTPR=lfS|Q;<5494;7?3==1CXZ_UU8gkprXyV?78;4?>0:802<H]]Z^X7j`uu]r[3:3>3:5=55;7;MVPUSS2me~xRP7=65>58602><6B[[PTV9`jssWxU309850?3;?11=G\^[YY4kotv\uZ?;<?0;2<>4498JJUSS2J6?;7>11597<?OIX\^1HLQFN=64>586;2>36D@_UU8SGLH;<>0;2<84498LQQVR\3NJSB[[<5594;713=21CXZ_UU8GFZIR\5><6=0>1:6;>JSSX\^1\1:8:1<21>2?2F__\XZ5PBMVP920294:86:5IORVP?GK]DEOI1=50?35?1<H]]Z^X7MNRS[LQQ:4294379H;456701=29=:?78;;00181?OIX\^1ECC@DD>7>5863?20:LONA@CB5>153>8:?695IORVP?IWEFNN0;4?>394B`=0c:8>xkhh912.64=?:22;86670968<C>?:23J>6O?2:C26>G5:2K8>6O;4:C?4;3<I5;;285N<03=1>G;9;4>7L2>3?78E9736<1J0<;15:C?53823H6:;3;4A=3;:0=F483586O31?78E9476<1J0??15:C?67823H69?3;4A=07:0=F4;?596O327<6?D:5?7?0M1<7>69B87?=87?0M1<6>59B87833H68295N<5<7?D:26=1J0;0;;@>4:1=F414?7L26>99BGDUDZLM<7LMFN=2=<>GDAG6:<364ABKM847902KHEC2>2?:8EFOI489546OLIO>20;><IJCE0<;18:C@MK:6>720MNGA<05=<>GDAG6:4364ABKM84?9?2KHEC2>>99BGLH;:9437LMFN=02:==FK@D7>?07;@AJJ944611JOD@325<;?DENF58>255NCHL?638?3HIBB1<8>99BGLH;:14j7LMFN=0:>58?3HIBB1<6>69BGLH;:7=0MNGA<2<4?DENF5>5;6OLIO>6:2=FK@D7:394ABKM82803HIBB1617:C@MK:>611JOB[[<1<:?DEH]]6:<374ABMVP976601JOB[[<00==>GDG\^7=>06;@ALQQ:6<730MNAZT=36:<=FKF__0<819:C@KPR;9>427LM@UU>2<;?<IJE^X1?6>99BGJSS48427LM@UU>14;?<IJE^X1<>>89BGJSS4;8556OLOTV?668>3HIDYY2=4?;8EFIR\58>245NCNWW870912KHCXZ326<:?DEH]]6943l4ABMVP94>29427LM@UU>1=;><IJE^X1<18:C@KPR;;720MNAZT=6=<>GDG\^79364ABMVP90902KHCXZ37?:8EFIR\52546OLOTV?=;1<IMNY0=06;@FGV97=87=0MIJ]<0<b?DBCZH6;6=07;@FGVD:76h1JHI\N<083:==FLMXJ0<0n;@FGVD:529437LJKR@>1:d=FLMXI0=4?>99B@ATE494j7LJKRC>2>58?3HNO^O2>>`9B@ATE4;0;255NDEPA87823HNYIJo4AMWNKAC;87k0MA[BOEG?5;g<IE_FCIK32?a8EISJGMO7?7>1a:COQHICM595m6OCULMGAWC@<2KYIJ??;@WWKWCTM]U[MYJJT69B[LHW]]>0N1>15:@?55823K6:=3;4B=31:0=E489596L315<6?G:6=7?0N1?9>69A841=87?0N1?8>59A84833K69295M<2<7?G:36=1I080;;C>5:1=E4>4?7O27>59A8<853KI37OMNSBPFC2=EK@D7<364BBKM846902HHEC2>1?:8FFOI488546LLIO>27;><JJCE0<:18:@@MK:6=720NNGA<04=e>DDAG6:;7>18:@@MK:6?7=0NNGA<0<4?GENF585;6LLIO>0:2=EK@D78394BBKM80803KIBB1817:@@MK:06>1IOD@38?58FFOI40437OM@UU>3:<=EKF__0<>19:@@KPR;98427OM@UU>26;?<JJE^X1?<>89AGJSS48>556LLOTV?508>3KIDYY2>6?`8FFIR\5;<6=06;CALQQ:6?720NNAZT=3=<>DDG\^7>364BBMVP95902HHCXZ34?:8FFIR\5?546LLOTV?2;><JJE^X1918:@@KPR;0720NNAZT=;=0>DUMN20NX]PIODL3>DXAGZ^X<5L4:A?4;3<K5;;285L<03=1>E;9;4>7N2>3?78G9736<1H0<;15:A?53823J6:;3;4C=3;:0=D483586M31?78G9476<1H0??15:A?67823J69?3;4C=07:0=D4;?596M327<6?F:5?7?0O1<7>49@87?9<2I7>3;4C=13:0=D4:;596M333<6?F:4;7?0O1=;>49@8639=2I7?;0:;B>03;3<K593285L<2;=0>E;;7?0O1:?>49@8179=2I78?0:;B>77;3<K5>?285L<57=1>E;<?4<7N2;7;2=1>E;<>4?7N2;>59@80833J6=295L<6<7?F:?6=1H040m;BCQV\EF[JCEo6MNRS[@EVEH]]=0OL\]YHLb?FGLine truncated
top/x300/coregen_dsp/hbdec2.v
-24109
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top/x300/coregen_dsp/hbdec2.veo
-79
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@@ -1,79 +0,0 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
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* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec2 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec2.v when simulating
// the core, hbdec2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbdec2.xco
-102
View File
@@ -1,102 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Dec 4 21:33:01 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb47.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=4
CSET component_name=hbdec2
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=100
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: b27c3487
top/x300/coregen_dsp/hbdec2.xise
-72
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@@ -1,72 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="hbdec2.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="hbdec2.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbdec2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="hbdec2.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbdec2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbdec2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-04T13:33:56" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8D4FB15FCAB64E0DEA10CDE0E19A7C80" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_dsp/hbdec2COEFF_auto0_0.mif
-9
View File
@@ -1,9 +0,0 @@
111111111111000010
000000000011000010
111111111001001000
000000001101010111
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2COEFF_auto0_1.mif
-9
View File
@@ -1,9 +0,0 @@
111111101000011111
000000100110101110
111111000011000100
000001011101100110
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2COEFF_auto0_2.mif
-9
View File
@@ -1,9 +0,0 @@
111101110000011101
000011100100101000
111001100001011000
010100010001000001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
-3
View File
@@ -1,3 +0,0 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec2_flist.txt
-19
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@@ -1,19 +0,0 @@
# Output products list for <hbdec2>
hbdec2.asy
hbdec2.gise
hbdec2.mif
hbdec2.ngc
hbdec2.v
hbdec2.veo
hbdec2.xco
hbdec2.xise
hbdec2COEFF_auto0_0.mif
hbdec2COEFF_auto0_1.mif
hbdec2COEFF_auto0_2.mif
hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
hbdec2_flist.txt
hbdec2_readme.txt
hbdec2_reload_addrfilt_decode_rom.mif
hbdec2_reload_order.txt
hbdec2_xmdf.tcl
hbdec2filt_decode_rom.mif
top/x300/coregen_dsp/hbdec2_readme.txt
-64
View File
@@ -1,64 +0,0 @@
The following files were generated for 'hbdec2' in directory
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbdec2.mif
* hbdec2_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbdec2.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbdec2.ngc
* hbdec2.v
* hbdec2.veo
* hbdec2COEFF_auto0_0.mif
* hbdec2COEFF_auto0_1.mif
* hbdec2COEFF_auto0_2.mif
* hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
* hbdec2_reload_addrfilt_decode_rom.mif
* hbdec2filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbdec2.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbdec2.asy
* hbdec2.mif
* hbdec2_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbdec2_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbdec2.gise
* hbdec2.xise
Deliver Readme:
Readme file for the IP.
* hbdec2_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbdec2_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif
-17
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@@ -1,17 +0,0 @@
000
100
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
top/x300/coregen_dsp/hbdec2_reload_order.txt
-25
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@@ -1,25 +0,0 @@
Reload index 0 = Index 16
Reload index 1 = Index 18
Reload index 2 = Index 20
Reload index 3 = Index 22
Reload index 4 = Index 8
Reload index 5 = Index 10
Reload index 6 = Index 12
Reload index 7 = Index 14
Reload index 8 = Index 0
Reload index 9 = Index 2
Reload index 10 = Index 4
Reload index 11 = Index 6
Reload index 12 = Index 23
Reload index 13 = Index 0
Reload index 14 = Index 0
Reload index 15 = Index 0
Reload index 16 = Index 0
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
top/x300/coregen_dsp/hbdec2_xmdf.tcl
-99
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@@ -1,99 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide hbdec2_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbdec2_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbdec2_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2
}
# ::hbdec2_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbdec2_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbdec2filt_decode_rom.mif
-17
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@@ -1,17 +0,0 @@
000
100
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
top/x300/coregen_dsp/hbdec3.asy
-61
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@@ -1,61 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbdec3
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[47:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[47:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbdec3.gise
-32
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@@ -1,32 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbdec3.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbdec3.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbdec3.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbdec3_reload_order.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_dsp/hbdec3.mif
-63
View File
@@ -1,63 +0,0 @@
111111111111011101
000000000000000000
000000000001011111
000000000000000000
111111111100111101
000000000000000000
000000000101100000
000000000000000000
111111110110111010
000000000000000000
000000001110001011
000000000000000000
111111101010110110
000000000000000000
000000011110100001
000000000000000000
111111010101000001
000000000000000000
000000111011100101
000000000000000000
111110101101111111
000000000000000000
000001110001100000
000000000000000000
111101011111001000
000000000000000000
000011110010000110
000000000000000000
111001011000110101
000000000000000000
010100010011111100
011111111111111111
010100010011111100
000000000000000000
111001011000110101
000000000000000000
000011110010000110
000000000000000000
111101011111001000
000000000000000000
000001110001100000
000000000000000000
111110101101111111
000000000000000000
000000111011100101
000000000000000000
111111010101000001
000000000000000000
000000011110100001
000000000000000000
111111101010110110
000000000000000000
000000001110001011
000000000000000000
111111110110111010
000000000000000000
000000000101100000
000000000000000000
111111111100111101
000000000000000000
000000000001011111
000000000000000000
111111111111011101
top/x300/coregen_dsp/hbdec3.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$0dg2~753-Xnzd}foo8#5+421).97 ?>;168456702:;<=>?01a8456789:;<=>?8:2345678820<=>?012A<>6789:;=8640123454302:;<=>?24:84567898N46>?012372><89:;<=:88:234567=<20<=>?0175<>6789:;9:640123451502:;<=>?78:84567893?46>?0123=0><89:;<=7I8:234567I>20<=>?01@1<>6789:;NI64012345E302:;<=>?CD:8456789N>46>?0123@F><89:;<=K:8:234567M?20<=>?01D2<>6789:;JO640123<567:2:?>6>72:2:5>7438$;>6??4:3345773821EC^ZT;@?52<76890=54FNQWW>GENF5;<6=0>4:3;>LHW]]0OMRGA<0594;703821EC^ZT;alacYcag6:;7>11492<?IR\Y__6OM@UU>23?699?1:47AZTQWW>AGXG\^7=:4?>0485=<H]]Z^X7JM_NWW841=87;97<4FNQWW>DBCZH6;6=0>2:39MKVR\3KOH_L30;2=5f=62@D[YY4lodd\bljsm{Uxia2?:1<23>7=AGZ^X7hflugq[vck490;2<;41;MVPUSS2jbjbRga<183:40<93E^X][[:bjbjZir|5:1<3?429914DG58;:::6<;:HLSQQ<CI]KTEC2=3;2=57=5<3CE\XZ5dhl?66<768?0>94FNQWW>aoiW8:7>>4?>07861<NFY__6iga_03?66<768?0>94FNQWW>aoiW887>>4?>07861<NFY__6iga_01?66<768?0>94FNQWW>aoiW8>7>>4?>07861<NFY__6iga_07?66<768?0>94FNQWW>aoiW8<7>>4?>06861<NFY__6iga_0>17?699=1987GAPTV9`lhX:5886=0>4:07>LHW]]0oecQ<<3194;733;>1EC^ZT;fjjZ2;::0;2<:4258JJUSS2mceS82=3;2=51=5<3CE\XZ5dhl\2944294:86<;:HLSQQ<cagU<0?=50?37?72=AGZ^X7jfn^:?66<768>0>94FNQWW>aoiW069?7>119910?IR\Y__6IO[A^MVP944294::6<;:NWWTPR=lfSd2=3;2=5<=5<3E^X][[:emvpZoX9969?7>118910?IR\Y__6iazt^k\54:5;3:5=45=4;MVPUSS2me~xRgP13>17?69901987AZTQWW>air|VcT=>2=3;2=5<=5<3E^X][[:emvpZoX9=69?7>118910?IR\Y__6iazt^k\50:5;3:5=45=4;MVPUSS2me~xRgP17>17?69911987AZTQWW>air|VcT=1<<:1<2<>432F__\XZ5dnww[lY54;91<3?7;369KPRW]]0ocxzPi^1?66<76820>94@UURVP?bh}}UbS92=3;2=5==5<3E^X][[:emvpZoX=5886=0>8:07>JSSX\^1hb{{_h]5875=87;37?:5OTVSQQ<cg|~TeR932283:4><:=0DYY^ZT;flqqYnW169?7>119910?IR\Y__6iazt^k\=944294:<6<::HLSQQ<C4;>1<3?=;38JJUSS2HNO^L2>:1<26>4=AGZ^X7OKDS@?5?699918<7GAPTV9E94>294:?6=?:HLSQQ<FK@D7>44?>07875<H]]Z^X7OLOTV?6<<768;0?7GAPTV9EABU4;0;2<943;KMTPR=KHXYUD@\EM>1>58682>36D@_UU8@811=87;?7965IORVP?BFW@D78:4?>0180=<NFY__6]MFN=64>586>2>36B[[PTV9@DYH]]6?;7>11797<?IR\Y__6ILPOTV?02<768;0854@UURVP?V;<>0;2<;4498LQQVR\3ZHCXZ34683:42<<10DYY^ZT;flqq:3?3:5=:5;8;MVPUSS2me~xR??<5594;703=21CXZ_UU8gkprX986?;7>11697<?IR\Y__6iazt^31811=87;<7965OTVSQQ<cg|~T=>2;7;2=52=303E^X][[:emvpZ734==1<3?8;5:9KPRW]]0ocxzP14>73?699>1?47AZTQWW>air|V;=09950?35?1>=G\^[YY4kotv\5920294::6:7:NWWTPR=lfS?2;7;2=53=303E^X][[:emvpZ5;<>0;2<84498LQQVR\3ndyyQ;<5594;713=21CXZ_UU8gkprX=5><6=0>6:6;>JSSX\^1hb{{_7>73?699?1?47AZTQWW>air|V=78:4?>0480=<H]]Z^X7j`uu];811=87;=7965OTVSQQ<cg|~T51:8:1<22>2?2F__\XZ5dnww[t:3?3:5=45;8;MVPUSS2me~xRP11>73?69901?47AZTQWW>air|V{T=<2;7;2=5<=303E^X][[:emvpZwX9;6?;7>11897<?IR\Y__6iazt^s\56:3?3:5=45;8;MVPUSS2me~xRP15>73?69901?47AZTQWW>air|V{T=82;7;2=5<=303E^X][[:emvpZwX9?6?;7>11997<?IR\Y__6iazt^s\5920294:46:7:NWWTPR=lfS|Q=<5594;7?3=21CXZ_UU8gkprXyV978:4?>0:80=<H]]Z^X7j`uu]r[1:3?3:5=55;8;MVPUSS2me~xRP5=64>58602>36B[[PTV9`jssWxU=09950?3;?1>=G\^[YY4kotv\uZ1;<>0;2<64498LQQVR\3ndyyQ~_9>73?69911?47AZTQWW>air|V{T51:8:1<26>2=AGZ^X7OKDSC?7?699;1?6D@_UU8B@ATE4:0;2<:44;KMTPR=IE_FCIK33;2=53=32F__\XZ5C@PQ]JSS4:0;255;F56701233<;?<95:55227>3=AGZ^X7GAMNFF81<7681=468NA@CBED7<?;1<><=47;KMTPR=GYGDHH29:1<1?2@b3>a8>8ziff;34(4631804=:4892;0>>A01805L<4A108E44<I;80M><4A568E969=2K7==0:;@>25;3<I5;9285N<01=1>G;9=4>7L2>5?78E9716<1J0<915:C?5=823H6:53:4A=3=1>G;:94>7L2=1?78E9456<1J0?=15:C?61823H6993;4A=05:0=F4;=596O329<4?D:513:596O328<7?D:56=1J0>0;;@>7:1=F4<4?7L29>59B82833H63295N<8<;?DEF[JXNK:5NCHL?4;><IJCE0<>18:C@MK:69720MNGA<00=<>GDAG6:?364ABKM842902KHEC2>5?:8EFOI48<546OLIO>23;><IJCE0<618:C@MK:617=0MNGA<0<;?DENF58;255NCHL?648?3HIBB1<=>99BGLH;::437LMFN=07:==FK@D7>807;@AJJ941611JOD@326<;?DENF5832l5NCHL?6<<7611JOD@328<4?DENF585;6OLIO>0:2=FK@D78394ABKM80803HIBB1817:C@MK:06>1JOD@38?58EFOI40437LM@UU>3:<=FKF__0<>19:C@KPR;98427LM@UU>26;?<IJE^X1?<>89BGJSS48>556OLOTV?508>3HIDYY2>6?;8EFIR\5;<245NCNWW84>912KHCXZ318<;?DEH]]6:245NCNWW876912KHCXZ320<:?DEH]]69>374ABMVP944601JOB[[<36==>GDG\^7>806;@ALQQ:5>730MNAZT=04:<=FKF__0?61b:C@KPR;:00;245NCNWW87?902KHCXZ32?:8EFIR\59546OLOTV?0;><IJE^X1;18:C@KPR;>720MNAZT=5=<>GDG\^74364ABMVP9?9?2KOH_2?>69B@AT;9730MIJ]<383:2=FLMX7>3o4AEFQE96=8720MIJ]A=2=e>GCL[K7=7>18:CG@WG;9720MIJ]A=0=e>GCL[K7?7>18:CG@WG;;7k0MIJ]B=294;><IMNYN1>1a:CG@WD;93:546OKDS@?5;><IMNYN1<1a:CG@WD;;3:546OKDS@?7;3<IMXNKl5NLTOL@@:76h1J@XC@DD>2:d=FD\GDHH2=>b9BHPKHLL686=0n;@NVIJBB4:4j7LBZMNFFV@A33HXNK<>4ATVLV@UB\VZJXIK[7:C\MKVR\=1I0=0:;C>24;3<J5;:285M<00=1>D;9:4>7O2>4?78F9726<1I0<817:@?52<76<1I0<914:@?5;2<J58586L33?68F929<2H793:4B=4=0>D;?7>0N1614:@?=;4<JJ20NNO\CSGD3>DDAG6;255MCHL?558?3KIBB1?>>99AGLH;9;437OMFN=30:==EK@D7=907;CAJJ972611IOD@317<b?GENF5;<6=07;CAJJ9706>1IOD@31?58FFOI4;4<7OMFN=1=3>DDAG6?2:5MCHL?1;1<JJCE0;08;CAJJ919?2HHEC27>69AGLH;1720NNAZT=2==>DDG\^7==06;CALQQ:69730NNAZT=31:<=EKF__0<=19:@@KPR;9=427OM@UU>21;?<JJE^X1?9>c9AGJSS48=1<374BBMVP970611IOB[[<0<;?GEH]]69255MCNWW868?3KIDYY2;>99AGJSS4<437OM@UU>5:==EKF__0:07;CALQQ:?611IOB[[<8<7?GTBO11IY^QFNGM4?GYNFY__=6M;;B>3:0=D48:596M310<6?F:6:7?0O1?<>49@8429=2I7=80:;B>22;3<K5;<285L<0:=1>E;904?7N2>>49@8769=2I7><0:;B>16;3<K588285L<36=1>E;:<4>7N2=6?78G9406<1H0?615:A?6<833J69285L<22=1>E;;84>7N2<2?78G9546<1H0>:15:A?70823J68:3;4C=14:0=Line truncated
top/x300/coregen_dsp/hbdec3.v
-20014
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File diff suppressed because it is too large. Load diff
top/x300/coregen_dsp/hbdec3.veo
-79
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/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbdec3 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [47 : 0] dout_1
.dout_2(dout_2)); // output [47 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbdec3.v when simulating
// the core, hbdec3. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbdec3.xco
-102
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@@ -1,102 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Dec 4 21:31:43 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb63.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=3
CSET component_name=hbdec3
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=48
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=50
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: 86e0fdc7
top/x300/coregen_dsp/hbdec3.xise
-72
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="hbdec3.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="hbdec3.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbdec3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="hbdec3.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbdec3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbdec3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-04T13:32:39" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0C4461115773DD979C3A5F377B8C29BF" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_dsp/hbdec3COEFF_auto0_0.mif
-17
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@@ -1,17 +0,0 @@
111111111111011101
000000000001011111
111111111100111101
000000000101100000
111111110110111010
000000001110001011
111111101010110110
000000011110100001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec3COEFF_auto0_1.mif
-17
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@@ -1,17 +0,0 @@
111111010101000001
000000111011100101
111110101101111111
000001110001100000
111101011111001000
000011110010000110
111001011000110101
010100010011111100
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
-3
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@@ -1,3 +0,0 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbdec3_flist.txt
-18
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@@ -1,18 +0,0 @@
# Output products list for <hbdec3>
hbdec3.asy
hbdec3.gise
hbdec3.mif
hbdec3.ngc
hbdec3.v
hbdec3.veo
hbdec3.xco
hbdec3.xise
hbdec3COEFF_auto0_0.mif
hbdec3COEFF_auto0_1.mif
hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
hbdec3_flist.txt
hbdec3_readme.txt
hbdec3_reload_addrfilt_decode_rom.mif
hbdec3_reload_order.txt
hbdec3_xmdf.tcl
hbdec3filt_decode_rom.mif
top/x300/coregen_dsp/hbdec3_readme.txt
-63
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@@ -1,63 +0,0 @@
The following files were generated for 'hbdec3' in directory
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbdec3.mif
* hbdec3_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbdec3.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbdec3.ngc
* hbdec3.v
* hbdec3.veo
* hbdec3COEFF_auto0_0.mif
* hbdec3COEFF_auto0_1.mif
* hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
* hbdec3_reload_addrfilt_decode_rom.mif
* hbdec3filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbdec3.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbdec3.asy
* hbdec3.mif
* hbdec3_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbdec3_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbdec3.gise
* hbdec3.xise
Deliver Readme:
Readme file for the IP.
* hbdec3_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbdec3_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbdec3_reload_addrfilt_decode_rom.mif
-17
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@@ -1,17 +0,0 @@
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
top/x300/coregen_dsp/hbdec3_reload_order.txt
-33
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@@ -1,33 +0,0 @@
Reload index 0 = Index 16
Reload index 1 = Index 18
Reload index 2 = Index 20
Reload index 3 = Index 22
Reload index 4 = Index 24
Reload index 5 = Index 26
Reload index 6 = Index 28
Reload index 7 = Index 30
Reload index 8 = Index 0
Reload index 9 = Index 2
Reload index 10 = Index 4
Reload index 11 = Index 6
Reload index 12 = Index 8
Reload index 13 = Index 10
Reload index 14 = Index 12
Reload index 15 = Index 14
Reload index 16 = Index 31
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
Reload index 24 = Index 0
Reload index 25 = Index 0
Reload index 26 = Index 0
Reload index 27 = Index 0
Reload index 28 = Index 0
Reload index 29 = Index 0
Reload index 30 = Index 0
Reload index 31 = Index 0
top/x300/coregen_dsp/hbdec3_xmdf.tcl
-95
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@@ -1,95 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide hbdec3_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbdec3_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbdec3_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec3
}
# ::hbdec3_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbdec3_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec3
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbdec3filt_decode_rom.mif
-17
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@@ -1,17 +0,0 @@
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
top/x300/coregen_dsp/hbint1.asy
-61
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@@ -1,61 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbint1
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[46:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[46:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbint1.gise
-32
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@@ -1,32 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbint1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbint1.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbint1.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbint1_reload_order.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_dsp/hbint1.mif
-63
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@@ -1,63 +0,0 @@
111111111111011101
000000000000000000
000000000001011111
000000000000000000
111111111100111101
000000000000000000
000000000101100000
000000000000000000
111111110110111010
000000000000000000
000000001110001011
000000000000000000
111111101010110110
000000000000000000
000000011110100001
000000000000000000
111111010101000001
000000000000000000
000000111011100101
000000000000000000
111110101101111111
000000000000000000
000001110001100000
000000000000000000
111101011111001000
000000000000000000
000011110010000110
000000000000000000
111001011000110101
000000000000000000
010100010011111100
011111111111111111
010100010011111100
000000000000000000
111001011000110101
000000000000000000
000011110010000110
000000000000000000
111101011111001000
000000000000000000
000001110001100000
000000000000000000
111110101101111111
000000000000000000
000000111011100101
000000000000000000
111111010101000001
000000000000000000
000000011110100001
000000000000000000
111111101010110110
000000000000000000
000000001110001011
000000000000000000
111111110110111010
000000000000000000
000000000101100000
000000000000000000
111111111100111101
000000000000000000
000000000001011111
000000000000000000
111111111111011101
top/x300/coregen_dsp/hbint1.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$32e`~753-Xnzd}foo8#5+421).97 ?>;168456702:;<=>?01a8456789:;<=>?8:2345678820<=>?012A<>6789:;=8640123454302:;<=>?24:84567898N46>?012372><89:;<=:88:234567=<20<=>?0175<>6789:;9:640123451502:;<=>?78:84567893?46>?0123=0><89:;<=7I8:234567I>20<=>?01@1<>6789:;NI64012345E302:;<=>?CD:8456789N>46>?0123@F><89:;<=K:8:234567M?20<=>?01D2<>6789:;JO640123<567:2:?>6>71:30?4(7:2;;86??0133?4>=AGZ^X7L31683:45<910BB][[:CAJJ970294:86?7:HLSQQ<CIVCE0<950?34?4>=AGZ^X7m`eg]gmk:6?3:5=85>8;MVPUSS2KIDYY2>7;2=53=603E^X][[:EC\KPR;9>0;2<84198LQQVR\3NISB[[<0594;75380BB][[:@FGVD:7294:>6?5IORVP?GCL[H7<7>11b92>LHW]]0hchhPfhnwawYtme6;6=0>7:39MKVR\3lb`yk}_rgo85<768?0=7AZTQWW>fnffVce0=4?>0485?IR\Y__6nfnn^mvp96=87;0>55=0@C14766>28?6D@_UU8GEQGXAG69?7>113910?OIX\^1hd`32283:43<:=0BB][[:ekm[46;::0;2<;4258JJUSS2mceS<?32283:43<:=0BB][[:ekm[44;::0;2<;4258JJUSS2mceS<=32283:43<:=0BB][[:ekm[42;::0;2<;4258JJUSS2mceS<;32283:43<:=0BB][[:ekm[40;::0;2<:4258JJUSS2mceS<2=3;2=51=5<3CE\XZ5dhl\6944294:86<;:HLSQQ<cagU80?=50?37?72=AGZ^X7jfn^6?66<768>0>94FNQWW>aoiW<69?7>115910?OIX\^1hd`P6=00>586<28?6D@_UU8gmkY04;91<3?;;369MKVR\3nbbR632283:42<:=0BB][[:ekm[<:5;3:5=55=4;MVPUSS2MK_MRAZT=00>586>28?6B[[PTV9`jssW`69?7>118910?IR\Y__6iazt^k\55:5;3:5=45=4;MVPUSS2me~xRgP10>17?69901987AZTQWW>air|VcT=?2=3;2=5<=5<3E^X][[:emvpZoX9:69?7>118910?IR\Y__6iazt^k\51:5;3:5=45=4;MVPUSS2me~xRgP14>17?69901987AZTQWW>air|VcT=;2=3;2=5==5<3E^X][[:emvpZoX95886=0>8:07>JSSX\^1hb{{_h]1875=87;37?:5OTVSQQ<cg|~TeR=32283:4><:=0DYY^ZT;flqqYnW=69?7>119910?IR\Y__6iazt^k\1944294:46<;:NWWTPR=lfSdQ9<3194;7?3;>1CXZ_UU8gkprXaV=7>>4?>0:861<H]]Z^X7j`uu]j[=:5;3:5=55=4;MVPUSS2me~xRgP9=00>586828>6D@_UU8G872=87;97?4FNQWW>DBCZH6:6=0>2:09MKVR\3KOH_L31;2=55=483CE\XZ5A=0:>586;29;6D@_UU8BGLH;:00;2<;4318LQQVR\3KHCXZ32883:47<;3CE\XZ5AEFQ87<768=0?7GAPTV9GDTUQ@DXIA2=:1<7?6G5I8>08:4@UURVP?bh}}6?:7>116973?IR\Y__6iazt^33810=87;<7995OTVSQQ<cg|~T=<2;6;2=52=3?3E^X][[:emvpZ754=<1<3?8;559KPRW]]0ocxzP12>72?699>1?;7AZTQWW>air|V;?09850?34?11=G\^[YY4kotv\50:3>3:5=:5;7;MVPUSS2me~xR?9<5494;713==1CXZ_UU8gkprX95>=6=0>6:64>JSSX\^1hb{{_3>72?699?1?;7AZTQWW>air|V978;4?>04802<H]]Z^X7j`uu]7810=87;=7995OTVSQQ<cg|~T91:9:1<22>202F__\XZ5dnww[3:3>3:5=;5;7;MVPUSS2me~xR934783:40<<>0DYY^ZT;flqqY?4=<1<3?9;559KPRW]]0ocxzP9=65>586>2><6B[[PTV9`jssWx6?:7>118973?IR\Y__6iazt^s\55:3>3:5=45;7;MVPUSS2me~xRP10>72?69901?;7AZTQWW>air|V{T=?2;6;2=5<=3?3E^X][[:emvpZwX9:6?:7>118973?IR\Y__6iazt^s\51:3>3:5=45;7;MVPUSS2me~xRP14>72?69901?;7AZTQWW>air|V{T=;2;6;2=5==3?3E^X][[:emvpZwX95>=6=0>8:64>JSSX\^1hb{{_p]1810=87;37995OTVSQQ<cg|~T}R=34783:4><<>0DYY^ZT;flqqYvW=6?:7>119973?IR\Y__6iazt^s\1921294:46:8:NWWTPR=lfS|Q9<5494;7?3==1CXZ_UU8gkprXyV=78;4?>0:802<H]]Z^X7j`uu]r[=:3>3:5=55;7;MVPUSS2me~xRP9=65>58682>36D@_UU8@811=87;87965IORVP?VDAG6?;7>11097<?IR\Y__6]2;7;2=50=303E^X][[:QALQQ:3?3:5=?5;:HLSQQ<FLMXJ0>4?>0080?OIX\^1MIJ]B=194;733=0BB][[:@NVIJBB4:0;2<844;MVPUSS2JKY^TAZT=194;><<O>?89:;4:7205><==;;==??4:7447743<0BB][[:HLNKAC;<3:5=68;;74@21=1IHK:7::4740356=02@D[YY4@PLMGA90=8780;Kk47j111q`ao0:;!??4859;<5>6<23?6D@_UU8GEZOI4091<3?9;869KPRW]]0OMRAZT=;0>586>23?6B[[PTV9@GYH]]62?7>12:C36>G6:2K9>6O<2:C70>G;87?0M1??>49B8479=2K7=?0:;@>27;3<I5;?285N<07=1>G;9?4>7L2>7?78E97?6<1J0<714:C?5;3<I58;285N<33=1>G;:;4>7L2=3?78E9436<1J0?;15:C?63823H69;3;4A=0;:2=F4;31<3;4A=0::1=F4;4?7L2<>59B81833H6>295N<7<7?D:06=1J050;;@>::==FKHYH^HI8;@AJJ96902KHEC2>0?:8EFOI48;546OLIO>26;><IJCE0<=18:C@MK:6<720MNGA<07=<>GDAG6::364ABKM841902KHEC2>8?:8EFOI4835;6OLIO>2:==FK@D7>=07;@AJJ946611JOD@323<;?DENF588255NCHL?618?3HIBB1<:>99BGLH;:?437LMFN=04:==FK@D7>50n;@AJJ94>29437LMFN=0::2=FK@D7>394ABKM86803HIBB1:17:C@MK:26>1JOD@36?58EFOI4>4<7LMFN=:=3>GDAG62255NCNWW858>3HIDYY2>0?;8EFIR\5;:245NCNWW844912KHCXZ312<:?DEH]]6:8374ABMVP972601JOB[[<04==>GDG\^7=:06;@ALQQ:60730MNAZT=3::==FKF__0<06;@ALQQ:58730MNAZT=02:<=FKF__0?<19:C@KPR;::427LM@UU>10;?<IJE^X1<:>89BGJSS4;<556OLOTV?628>3HIDYY2=8?`8EFIR\5826=06;@ALQQ:51720MNAZT=0=<>GDG\^7?364ABMVP92902KHCXZ35?:8EFIR\5<546OLOTV?3;><IJE^X1618:C@KPR;17=0MIJ]<1<4?DBCZ5;556OKDS>1>5803HNO^1<1a:CG@WG;83:546OKDSC?4;g<IMNYM1?50?:8EABUI5;546OKDSC?6;g<IMNYM1=50?:8EABUI595m6OKDS@?4?6902KOH_L30?c8EABUJ5;1<364AEFQF97902KOH_L32?c8EABUJ591<364AEFQF959=2KO^HIn;@NVIJBB494j7LBZMNFF848f3HF^ABJJ<3<`?DJREFNN0>4?>`9BHPKHLL682l5NLTOL@@TBO=1J^HI>0:CVPJTB[L^T\LZKEU58EZOIX\^?7O2?>49A8469=2H7=<0:;C>26;3<J5;8285M<06=1>D;9<4>7O2>6?58F970294>7O2>7?68F979<2H7>3:4B=1=0>D;<7>0N1;14:@?2;2<J5=586L38?68F9?9:2HJ>6LL8:@@EVEUMN=0NNGA<1<;?GENF5;;255MCHL?548?3KIBB1?=>99AGLH;9:437OMFN=37:==EK@D7=807;CAJJ9716h1IOD@31683:==EK@D7=:08;CAJJ979?2HHEC2=>69AGLH;;7=0NNGA<5<4?GENF5?5;6LLIO>5:2=EK@D7;394BBKM8=803KIBB1718:@@KPR;8730NNAZT=33:<=EKF__0<?19:@@KPR;9;427OM@UU>27;?<JJE^X1?;>89AGJSS48?556LLOTV?538e3KIDYY2>7;2==>DDG\^7=:07;CALQQ:6611IOB[[<3<;?GEH]]68255MCNWW818?3KIDYY2:>99AGJSS4?437OM@UU>4:==EKF__0507;CALQQ:>6=1I^HI7;CWP[LHAG>1ISD@_UU38G1=D494>7N2>0?78G9766<1H0<<15:A?56823J6:83;4C=36:0=D48<596M316<6?F:607?0O1?6>59@84823J69<3;4C=02:0=D4;8596M322<6?F:5<7?0O1<:>49@8709=2I7>:0:;B>1<;3<K582295L<3<6?F:487?0O1=>>49@8649=2I7?>0:;B>00;3<K59>285L<24=1>ELine truncated
top/x300/coregen_dsp/hbint1.v
-20302
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File diff suppressed because it is too large. Load diff
top/x300/coregen_dsp/hbint1.veo
-79
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@@ -1,79 +0,0 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbint1 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbint1.v when simulating
// the core, hbint1. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbint1.xco
-102
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@@ -1,102 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu Dec 5 22:34:55 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb63.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=3
CSET component_name=hbint1
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=1
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Interpolation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=2
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.43
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=25
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.57
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: 4991bbb9
top/x300/coregen_dsp/hbint1.xise
-72
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="hbint1.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="hbint1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbint1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="hbint1.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbint1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbint1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-05T14:35:52" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9048954B661F64BB56A3564785FF4CAD" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_dsp/hbint1COEFF_auto0_0.mif
-17
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@@ -1,17 +0,0 @@
111111111111011101
000000000001011111
111111111100111101
000000000101100000
111111110110111010
000000001110001011
111111101010110110
000000011110100001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint1COEFF_auto0_1.mif
-17
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@@ -1,17 +0,0 @@
111111010101000001
000000111011100101
111110101101111111
000001110001100000
111101011111001000
000011110010000110
111001011000110101
010100010011111100
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint1COEFF_auto0_2.mif
-9
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@@ -1,9 +0,0 @@
111110111010101110
000001110000011001
111100110001111010
001010001000000110
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint1COEFF_auto_HALFBAND_CENTRE0.mif
-3
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@@ -1,3 +0,0 @@
011111111111111111
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint1_flist.txt
-18
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@@ -1,18 +0,0 @@
# Output products list for <hbint1>
hbint1.asy
hbint1.gise
hbint1.mif
hbint1.ngc
hbint1.v
hbint1.veo
hbint1.xco
hbint1.xise
hbint1COEFF_auto0_0.mif
hbint1COEFF_auto0_1.mif
hbint1COEFF_auto_HALFBAND_CENTRE0.mif
hbint1_flist.txt
hbint1_readme.txt
hbint1_reload_addrfilt_decode_rom.mif
hbint1_reload_order.txt
hbint1_xmdf.tcl
hbint1filt_decode_rom.mif
top/x300/coregen_dsp/hbint1_readme.txt
-63
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@@ -1,63 +0,0 @@
The following files were generated for 'hbint1' in directory
/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* hbint1.mif
* hbint1_reload_order.txt
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* hbint1.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* hbint1.ngc
* hbint1.v
* hbint1.veo
* hbint1COEFF_auto0_0.mif
* hbint1COEFF_auto0_1.mif
* hbint1COEFF_auto_HALFBAND_CENTRE0.mif
* hbint1_reload_addrfilt_decode_rom.mif
* hbint1filt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* hbint1.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* hbint1.asy
* hbint1.mif
* hbint1_reload_order.txt
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* hbint1_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* hbint1.gise
* hbint1.xise
Deliver Readme:
Readme file for the IP.
* hbint1_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* hbint1_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/x300/coregen_dsp/hbint1_reload_addrfilt_decode_rom.mif
-17
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@@ -1,17 +0,0 @@
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
top/x300/coregen_dsp/hbint1_reload_order.txt
-33
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@@ -1,33 +0,0 @@
Reload index 0 = Index 16
Reload index 1 = Index 18
Reload index 2 = Index 20
Reload index 3 = Index 22
Reload index 4 = Index 24
Reload index 5 = Index 26
Reload index 6 = Index 28
Reload index 7 = Index 30
Reload index 8 = Index 0
Reload index 9 = Index 2
Reload index 10 = Index 4
Reload index 11 = Index 6
Reload index 12 = Index 8
Reload index 13 = Index 10
Reload index 14 = Index 12
Reload index 15 = Index 14
Reload index 16 = Index 31
Reload index 17 = Index 0
Reload index 18 = Index 0
Reload index 19 = Index 0
Reload index 20 = Index 0
Reload index 21 = Index 0
Reload index 22 = Index 0
Reload index 23 = Index 0
Reload index 24 = Index 0
Reload index 25 = Index 0
Reload index 26 = Index 0
Reload index 27 = Index 0
Reload index 28 = Index 0
Reload index 29 = Index 0
Reload index 30 = Index 0
Reload index 31 = Index 0
top/x300/coregen_dsp/hbint1_xmdf.tcl
-95
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# The package naming convention is <core_name>_xmdf
package provide hbint1_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::hbint1_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::hbint1_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name hbint1
}
# ::hbint1_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::hbint1_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1COEFF_auto0_0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1COEFF_auto0_1.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1COEFF_auto_HALFBAND_CENTRE0.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1_reload_addrfilt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1_reload_order.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbint1filt_decode_rom.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbint1
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen_dsp/hbint1filt_decode_rom.mif
-17
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@@ -1,17 +0,0 @@
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
top/x300/coregen_dsp/hbint2.asy
-61
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@@ -1,61 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 hbint2
RECTANGLE Normal 32 32 544 2048
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName nd
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din_1[23:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName din_2[23:0]
PINATTR Polarity IN
LINE Normal 0 848 32 848
PIN 0 848 LEFT 36
PINATTR PinName coef_ld
PINATTR Polarity IN
LINE Normal 0 880 32 880
PIN 0 880 LEFT 36
PINATTR PinName coef_we
PINATTR Polarity IN
LINE Wide 0 912 32 912
PIN 0 912 LEFT 36
PINATTR PinName coef_din[17:0]
PINATTR Polarity IN
LINE Normal 0 1008 32 1008
PIN 0 1008 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 0 1040 32 1040
PIN 0 1040 LEFT 36
PINATTR PinName ce
PINATTR Polarity IN
LINE Normal 0 1072 32 1072
PIN 0 1072 LEFT 36
PINATTR PinName sclr
PINATTR Polarity IN
LINE Wide 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName dout_1[46:0]
PINATTR Polarity OUT
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName dout_2[46:0]
PINATTR Polarity OUT
LINE Normal 576 1840 544 1840
PIN 576 1840 RIGHT 36
PINATTR PinName rfd
PINATTR Polarity OUT
LINE Normal 576 1872 544 1872
PIN 576 1872 RIGHT 36
PINATTR PinName rdy
PINATTR Polarity OUT
LINE Normal 576 1904 544 1904
PIN 576 1904 RIGHT 36
PINATTR PinName data_valid
PINATTR Polarity OUT
top/x300/coregen_dsp/hbint2.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="hbint2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="hbint2.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="hbint2.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="hbint2_reload_order.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen_dsp/hbint2.mif
-47
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@@ -1,47 +0,0 @@
111111111111000010
000000000000000000
000000000011000010
000000000000000000
111111111001001000
000000000000000000
000000001101010111
000000000000000000
111111101000011111
000000000000000000
000000100110101110
000000000000000000
111111000011000100
000000000000000000
000001011101100110
000000000000000000
111101110000011101
000000000000000000
000011100100101000
000000000000000000
111001100001011000
000000000000000000
010100010001000001
011111111111111111
010100010001000001
000000000000000000
111001100001011000
000000000000000000
000011100100101000
000000000000000000
111101110000011101
000000000000000000
000001011101100110
000000000000000000
111111000011000100
000000000000000000
000000100110101110
000000000000000000
111111101000011111
000000000000000000
000000001101010111
000000000000000000
111111111001001000
000000000000000000
000000000011000010
000000000000000000
111111111111000010
top/x300/coregen_dsp/hbint2.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$36bb~753-Xnzd}foo8#5+421).97 ?>;168456702:;<=>?01a8456789:;<=>?8:2345678820<=>?0121<>6789:;<>640123456302:;<=>?04:8456789:=46>?012342><89:;<=>78:2345678020<=>?012B<>6789:;<O640123456D02:;<=>?0E:8456789:M46>?0163454<8=;0=>5>.108552<99:;==5>8;KMTPR=J5;<6=0>3:3;>LHW]]0IOD@31683:42<910BB][[:EC\MK:6?3:5=:5>8;KMTPR=kfomSiga<0594;723821CXZ_UU8AGJSS48=1<3?9;0:9KPRW]]0OMRAZT=34>586>2;36B[[PTV9@GYH]]6:;7>11392>LHW]]0JHI\N<183:44<93CE\XZ5AEFQF96=87;h7<4FNQWW>fibnVlb`yk}_rgo85<768=0=7GAPTV9bljsm{Uxia2?:1<21>7=G\^[YY4lh`l\mk:7294::6?5OTVSQQ<d`hdTcxz30;2=5>4?3;:JM?>=004861<NFY__6IO[A^KM875=87;97?:5IORVP?bnf5886=0>5:07>LHW]]0oecQ>0=00>586=28?6D@_UU8gmkY695886=0>5:07>LHW]]0oecQ>2=00>586=28?6D@_UU8gmkY6;5886=0>5:07>LHW]]0oecQ>4=00>586=28?6D@_UU8gmkY6=5886=0>5:07>LHW]]0oecQ>6=00>586<28?6D@_UU8gmkY64;91<3?;;369MKVR\3nbbR<32283:42<:=0BB][[:ekm[6:5;3:5=95=4;KMTPR=l`dT81<<:1<20>432@D[YY4kio]6875=87;?7?:5IORVP?bnfV<7>>4?>06861<NFY__6iga_6>17?699=1987GAPTV9`lhX05886=0>4:07>LHW]]0oecQ6<3194;7?3;>1CXZ_UU8GEQGXG\^7>>4?>04861<H]]Z^X7j`uu]j875=87;27?:5OTVSQQ<cg|~TeR??<3194;7>3;>1CXZ_UU8gkprXaV;:0?=50?3:?72=G\^[YY4kotv\mZ754;91<3?6;369KPRW]]0ocxzPi^30875=87;27?:5OTVSQQ<cg|~TeR?;<3194;7>3;>1CXZ_UU8gkprXaV;>0?=50?3:?72=G\^[YY4kotv\mZ714;91<3?7;369KPRW]]0ocxzPi^3?66<76820>94@UURVP?bh}}UbS?2=3;2=5==5<3E^X][[:emvpZoX;5886=0>8:07>JSSX\^1hb{{_h]7875=87;37?:5OTVSQQ<cg|~TeR;32283:4><:=0DYY^ZT;flqqYnW?69?7>119910?IR\Y__6iazt^k\3944294:46<;:NWWTPR=lfSdQ7<3194;7?3;>1CXZ_UU8gkprXaV37>>4?>02860<NFY__6I2=4;2=54=52@D[YY4NDEP?5?699;196D@_UU8B@ATF480;2<<42;KMTPR=IMNYN1?50?33?66=AGZ^X7O32883:45<;90BB][[:@AJJ94>294:96=?:NWWTPR=IJE^X1<6:1<26>5=AGZ^X7OKDSC?6?699;186D@_UU8B@ATE4;0;2<943;KMTPR=KHXYUD@\EM>1>5833:K9M?5;006802<H]]Z^X7j`uu>72?699>1?;7AZTQWW>air|V;;09850?34?11=G\^[YY4kotv\54:3>3:5=:5;7;MVPUSS2me~xR?=<5494;703==1CXZ_UU8gkprX9:6?:7>116973?IR\Y__6iazt^37810=87;<7995OTVSQQ<cg|~T=82;6;2=52=3?3E^X][[:emvpZ714=<1<3?9;559KPRW]]0ocxzP1=65>586>2><6B[[PTV9`jssW;6?:7>117973?IR\Y__6iazt^1?03<768<08:4@UURVP?bh}}U?09850?35?11=G\^[YY4kotv\1921294::6:8:NWWTPR=lfS;2;6;2=53=3?3E^X][[:emvpZ1;<?0;2<84468LQQVR\3ndyyQ7<5494;713==1CXZ_UU8gkprX15>=6=0>6:64>JSSX\^1hb{{_p>72?69901?;7AZTQWW>air|V{T==2;6;2=5<=3?3E^X][[:emvpZwX986?:7>118973?IR\Y__6iazt^s\57:3>3:5=45;7;MVPUSS2me~xRP12>72?69901?;7AZTQWW>air|V{T=92;6;2=5<=3?3E^X][[:emvpZwX9<6?:7>118973?IR\Y__6iazt^s\53:3>3:5=55;7;MVPUSS2me~xRP1=65>58602><6B[[PTV9`jssWxU909850?3;?11=G\^[YY4kotv\uZ5;<?0;2<64468LQQVR\3ndyyQ~_5>72?69911?;7AZTQWW>air|V{T91:9:1<2<>202F__\XZ5dnww[tY14=<1<3?7;559KPRW]]0ocxzPq^5?03<768208:4@UURVP?bh}}UzS52;6;2=5==3?3E^X][[:emvpZwX15>=6=0>0:6;>LHW]]0H09950?30?1>=AGZ^X7^LIO>73?69981?47AZTQWW>U:3?3:5=85;8;MVPUSS2YIDYY2;7;2=51=32@D[YY4NLTOL@@:4294::6:5OTVSQQ<DI[XRCXZ33;2=<>2A<=>?89:45063<>3399;;==:4562156=22@D[YY4FNLMGA92=87;0:9596B47?3GFI81<869:2130?2<NFY__6B^BOEG?2?69:2=Mi69d337wbca>89'9=66;;9:3<42<1=0BB][[:EC\MK:>;3:5=;564;MVPUSS2MKTCXZ39283:40<1=0DYY^ZT;FA[JSS4091<3<4A108E44<I;80M><4A568E969=2K7==0:;@>25;3<I5;9285N<01=1>G;9=4>7L2>5?78E9716<1J0<915:C?5=823H6:53:4A=3=1>G;:94>7L2=1?78E9456<1J0?=15:C?61823H6993;4A=05:0=F4;=596O329<4?D:513:596O328<7?D:56=1J0>0;;@>7:1=F4<4?7L29>59B82833H63295N<8<;?DEF[JXNK:5NCHL?4;><IJCE0<>18:C@MK:69720MNGA<00=<>GDAG6:?364ABKM842902KHEC2>5?:8EFOI48<546OLIO>23;><IJCE0<618:C@MK:617=0MNGA<0<;?DENF58;255NCHL?648?3HIBB1<=>99BGLH;::437LMFN=07:==FK@D7>807;@AJJ941611JOD@326<;?DENF5832l5NCHL?6<<7611JOD@328<4?DENF585;6OLIO>0:2=FK@D78394ABKM80803HIBB1817:C@MK:06>1JOD@38?58EFOI40437LM@UU>3:<=FKF__0<>19:C@KPR;98427LM@UU>26;?<IJE^X1?<>89BGJSS48>556OLOTV?508>3HIDYY2>6?;8EFIR\5;<245NCNWW84>912KHCXZ318<;?DEH]]6:245NCNWW876912KHCXZ320<:?DEH]]69>374ABMVP944601JOB[[<36==>GDG\^7>806;@ALQQ:5>730MNAZT=04:<=FKF__0?61b:C@KPR;:00;245NCNWW87?902KHCXZ32?:8EFIR\59546OLOTV?0;><IJE^X1;18:C@KPR;>720MNAZT=5=<>GDG\^74364ABMVP9?9?2KOH_2?>89B@AT;93:5;6OKDS>2:d=FLMXJ0=4?>99B@ATF494j7LJKR@>2>58?3HNO^L2>>`9B@ATF4;0;255NDEPB878f3HNO^O2?:1<;?DBCZK6;2l5NDEPA84<7611JHI\M<0<b?DBCZK696=07;@FGVG:56<1JH_KHa:COQHICM5:5m6OCULMGA979i2KGY@AKE=0=g>GK]DEOI1=50?c8EISJGMO7?3o4AMWNKACUMN>0M_KH119BQQIUMZO_S]O[DDV4?DYNFY__86L30?78F9776<1I0<?15:@?57823K6:?3;4B=37:0=E48?596L317<4?G:6?3:596L316<7?G:66=1I0?0;;C>0:1=E4=4?7O2:>59A83833K6<295M<9<7?G:>6;1IM?5MC99AGDUDZLM<7OMFN=2=<>DDAG6:<364BBKM847902HHEC2>2?:8FFOI489546LLIO>20;><JJCE0<;18:@@MK:6>7k0NNGA<0594;><JJCE0<917:@@MK:66>1IOD@32?58FFOI4:4<7OMFN=6=3>DDAG6>2:5MCHL?2;1<JJCE0:08;CAJJ9>9?2HHEC26>99AGJSS49427OM@UU>24;?<JJE^X1?>>89AGJSS488556LLOTV?568>3KIDYY2>4?;8FFIR\5;>245MCNWW8409j2HHCXZ31683:<=EKF__0<918:@@KPR;9720NNAZT=0=<>DDG\^7?364BBMVP92902HHCXZ35?:8FFIR\5<546LLOTV?3;><JJE^X1618:@@KPR;17>0N_KH8:@VWZOINF=0NRGAPTV2?F2<K5:596M311<6?F:697?0O1?=>49@8459=2I7=90:;B>21;3<K5;=285L<05=1>E;914>7N2>9?68G979=2I7>=0:;B>15;3<K589285L<31=1>E;:=4>7N2=5?78G9416<1H0?915:A?6=823J6953:4C=0=1>E;;94>7N2<1?78G9556<1H0>=15:A?71823J6893;4C=15:0=D4:=596M339<6?F:417>0O1=15:A?05823J6?=3;4C=61:0=D4=9596M345<6?F:3=7?0O1:9>69@811=87?0O1:8>59@81833J6>295L<7<7?F:06=1H050;;B>::g=DI[XROL]LIOa8GDTUQJKXOB[[7:ABVW_Line truncated
top/x300/coregen_dsp/hbint2.v
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top/x300/coregen_dsp/hbint2.veo
-79
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/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// Generated from component ID: xilinx.com:ip:fir_compiler:5.0
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
hbint2 YourInstanceName (
.sclr(sclr), // input sclr
.clk(clk), // input clk
.ce(ce), // input ce
.nd(nd), // input nd
.coef_ld(coef_ld), // input coef_ld
.coef_we(coef_we), // input coef_we
.coef_din(coef_din), // input [17 : 0] coef_din
.rfd(rfd), // output rfd
.rdy(rdy), // output rdy
.data_valid(data_valid), // output data_valid
.din_1(din_1), // input [23 : 0] din_1
.din_2(din_2), // input [23 : 0] din_2
.dout_1(dout_1), // output [46 : 0] dout_1
.dout_2(dout_2)); // output [46 : 0] dout_2
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file hbint2.v when simulating
// the core, hbint2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen_dsp/hbint2.xco
-102
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Dec 6 01:34:46 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=200
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./hb47.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=true
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Half_Band
CSET coefficient_width=18
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=4
CSET component_name=hbint2
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=24
CSET decimation_rate=1
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Interpolation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=true
CSET has_data_valid=true
CSET has_nd=true
CSET has_sclr=true
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=2
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=2
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Full_Precision
CSET output_width=47
CSET passband_max=0.41
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=50
CSET sampleperiod=1
CSET sclr_deterministic=true
CSET stopband_max=1.0
CSET stopband_min=0.59
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T05:23:34Z
# END Extra information
GENERATE
# CRC: a3f01bd
top/x300/coregen_dsp/hbint2.xise
-72
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="hbint2.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="hbint2.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|hbint2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="hbint2.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/hbint2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="hbint2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-05T17:35:41" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D8426CFC4E2E1B6F70716358AFC4E1A1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen_dsp/hbint2COEFF_auto0_0.mif
-9
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111111111111000010
000000000011000010
111111111001001000
000000001101010111
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint2COEFF_auto0_1.mif
-9
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@@ -1,9 +0,0 @@
111111101000011111
000000100110101110
111111000011000100
000001011101100110
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint2COEFF_auto0_2.mif
-9
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@@ -1,9 +0,0 @@
111101110000011101
000011100100101000
111001100001011000
010100010001000001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
top/x300/coregen_dsp/hbint2COEFF_auto_HALFBAND_CENTRE0.mif
-3
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@@ -1,3 +0,0 @@
011111111111111111
000000000000000000
000000000000000000
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