Removed copy of FPGA source files.
Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
@@ -1,45 +0,0 @@
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#!/bin/bash
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iterations=1
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directory="."
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targets=""
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name=""
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outdir=${PWD}
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for arg in "$@"; do
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if [[ $arg == "--help" ]]; then
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echo "Usage: batch-build [options] targets"
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echo "Options:"
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echo " --runs=N [1] Build the specified targets N times"
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echo " --dir=<dir> [.] Makefile directory"
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echo " --name=<name> [<empty>] Name of this batch job. Used as a prefix for build output"
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echo " --help Print the message and exit"
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echo ""
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exit 0
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elif [[ $arg =~ "--runs="([0-9]+) ]]; then
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iterations=${BASH_REMATCH[1]}
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elif [[ $arg =~ "--dir="(.+) ]]; then
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directory=${BASH_REMATCH[1]}
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elif [[ $arg =~ "--name="(.+) ]]; then
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name=${BASH_REMATCH[1]}"_"
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else
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targets=$targets$arg" "
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fi
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done
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cd $directory >/dev/null 2>&1
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if [ $? -ne 0 ]; then
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echo "ERROR: Could not cd to $directory"
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exit
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fi
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for i in $(seq 1 $iterations); do
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make $targets
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if [ $? -ne 0 ]; then
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echo "ERROR: Build Failed!!! Stopping batch build."
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exit
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fi
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cp -rf build ${outdir}/${name}batch-build_$(date +'%Y-%m-%d_%H-%M-%S')
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make clean
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done
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@@ -1,62 +0,0 @@
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#!/usr/bin/python
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import sys
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import os
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import struct
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def flip32(data):
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sl = struct.Struct('<I')
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sb = struct.Struct('>I')
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b = buffer(data)
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d = bytearray(len(data))
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for offset in xrange(0, len(data), 4):
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sb.pack_into(d, offset, sl.unpack_from(b, offset)[0])
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return d
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import argparse
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parser = argparse.ArgumentParser(description='Convert FPGA bit files to raw bin format suitable for flashing')
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parser.add_argument('-f', '--flip', dest='flip', action='store_true', default=False, help='Flip 32-bit endianess (needed for Zynq)')
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parser.add_argument("bitfile", help="Input bit file name")
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parser.add_argument("binfile", help="Output bin file name")
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args = parser.parse_args()
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short = struct.Struct('>H')
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ulong = struct.Struct('>I')
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bitfile = open(args.bitfile, 'rb')
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l = short.unpack(bitfile.read(2))[0]
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if l != 9:
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raise Exception, "Missing <0009> header (0x%x), not a bit file" % l
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bitfile.read(l)
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l = short.unpack(bitfile.read(2))[0]
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d = bitfile.read(l)
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if d != 'a':
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raise Exception, "Missing <a> header, not a bit file"
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l = short.unpack(bitfile.read(2))[0]
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d = bitfile.read(l)
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print "Design name:", d
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KEYNAMES = {'b': "Partname", 'c': "Date", 'd': "Time"}
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while 1:
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k = bitfile.read(1)
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if not k:
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raise Exception, "unexpected EOF"
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elif k == 'e':
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l = ulong.unpack(bitfile.read(4))[0]
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print "found binary data:", l
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d = bitfile.read(l)
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if args.flip:
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d = flip32(d)
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open(args.binfile, 'wb').write(d)
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break
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elif k in KEYNAMES:
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l = short.unpack(bitfile.read(2))[0]
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d = bitfile.read(l)
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print KEYNAMES[k], d
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else:
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print "Unexpected key: ", k
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l = short.unpack(bitfile.read(2))[0]
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d = bitfile.read(l)
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@@ -1,62 +0,0 @@
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#!/usr/bin/env python
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#
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# Copyright 2010 Ettus Research LLC
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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# Description:
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# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
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# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
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import sys
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import re
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if __name__=='__main__':
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if len(sys.argv) == 2:
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print "Usage: %s <top level Verilog file> <pin definition UCF>"
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sys.exit(-1)
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verilog_filename = sys.argv[1]
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ucf_filename = sys.argv[2]
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verilog_file = open(verilog_filename, 'r')
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ucf_file = open(ucf_filename, 'r')
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verilog_iolist = list()
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ucf_iolist = list()
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#read in all input, inout, and output declarations and compile a list
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for line in verilog_file:
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for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
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verilog_iolist.append(match)
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for line in ucf_file:
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m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
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if m is not None:
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ucf_iolist.append(m.group(1))
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#now find corresponding matches and error when you don't find one
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#we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
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err = False
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for item in verilog_iolist:
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if item not in ucf_iolist:
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print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
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err = True
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if err:
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sys.exit(-1)
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print "No errors found."
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sys.exit(0)
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@@ -1,37 +0,0 @@
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#!/usr/bin/env python
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#
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# Copyright 2011-2012 Ettus Research LLC
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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import sys
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import re
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def print_timing_constraint_summary(twr_file):
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output = ""
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keep = False
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done = False
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try: open(twr_file)
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except IOError:
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print "cannot open or find %s; no timing summary to print!"%twr_file
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exit(-1)
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for line in open(twr_file).readlines():
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if 'Derived Constraint Report' in line: keep = True
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if 'constraint' in line and 'met' in line: done = True
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if not keep and done: keep = True
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if keep: output += line
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if done: break
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print("\n\n"+output)
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if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])
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