miegl/b210-k7-fpga
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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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top/b200/planahead/planahead.data/sources_1/fileset.xml
-26
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@@ -1,26 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
<Attr Name="ImportTime" Val="1359508205"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/coregen/fifo_4k_2clk.ngc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../coregen/fifo_4k_2clk.ngc"/>
<Attr Name="ImportTime" Val="1359144134"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="GateLvl"/>
<Option Name="TopModule" Val="b200"/>
</Config>
</FileSet>
</DARoots>