Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
File diff suppressed because it is too large Load Diff
@@ -1,25 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
<Attr Name="ImportTime" Val="1358988004"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
<Attr Name="ImportTime" Val="1359506480"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>
@@ -1,20 +0,0 @@
<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE14">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
<Step Id="bitgen">
</Step>
</Strategy>
@@ -1,25 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
<Attr Name="ImportTime" Val="1358988004"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
<Attr Name="ImportTime" Val="1359506480"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>
@@ -1,20 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_out" Type="Constrs" RelSrcDir="$PRUNDIR/impl_1/.constrs">
<File Path="$PRUNDIR/impl_1/.constrs/b200.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PRUNDIR/impl_1/.constrs/timing.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>
@@ -1,20 +0,0 @@
<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE14">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
<Step Id="bitgen">
</Step>
</Strategy>
@@ -1,18 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
<Attr Name="ImportTime" Val="1359508205"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="b200"/>
</Config>
</FileSet>
</DARoots>
@@ -1,30 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="8">
<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx75fgg484-3" LaunchPart="xc6slx75fgg484-3" ConstrsSet="constrs_1" Description="Imported on Tue Jan 29 17:25:57 2013" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1359509156" Reconstructed="TRUE">
<File Type="MAP-PSR" Name="b200.psr"/>
<File Type="PA-EDIF" Name="b200.edf"/>
<File Type="PAR-NCD" Name="b200.ncd"/>
<File Type="PA-UCF" Name="b200.ucf"/>
<File Type="PAR-PAD" Name="b200_routed_pad.txt"/>
<File Type="PAR-PAR" Name="b200_routed.par"/>
<File Type="PAR-UNR" Name="b200_routed.unroutes"/>
<File Type="BG-BIT" Name="b200.bit"/>
<File Type="BG-DRC" Name="b200.drc"/>
<File Type="PA-CONSTRSDIR" Name=".constrs"/>
<File Type="BG-BGN" Name="b200.bgn"/>
<File Type="TRCE-TWR" Name="b200.twr"/>
<File Type="TRCE-TWX" Name="b200.twx"/>
<File Type="XDL-XDL" Name="b200.xdl"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<File Type="WBT-LOG" Name="webtalk.log"/>
<File Type="RUN-SRCS" Name="$PDATADIR/runs/impl_1/sources.xml"/>
<File Type="RUN-CONSTRS" Name="$PDATADIR/runs/impl_1/constrs_in.xml"/>
<File Type="RUN-STRAT" Name="$PDATADIR/runs/impl_1/impl_1.psg"/>
<File Type="NGDB-NGD" Name="b200.ngd"/>
<File Type="NGDB-BLD" Name="b200.bld"/>
<File Type="MAP-NCD" Name="b200.ncd"/>
<File Type="MAP-MRP" Name="b200.mrp"/>
<File Type="MAP-MAP" Name="b200.map"/>
</Run>
</Runs>
@@ -1,10 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</DARoots>
@@ -1,26 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
<Attr Name="ImportTime" Val="1359508205"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/coregen/fifo_4k_2clk.ngc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../coregen/fifo_4k_2clk.ngc"/>
<Attr Name="ImportTime" Val="1359144134"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="GateLvl"/>
<Option Name="TopModule" Val="b200"/>
</Config>
</FileSet>
</DARoots>
@@ -1,12 +0,0 @@
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@@ -1,3 +0,0 @@
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eof:
@@ -1,38 +0,0 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Jan 29 17:42:17 2013">
<section name="Project Information" visible="false">
<property name="ProjectID" value="a2486f6b8cdf4e77be535de080ad1097" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
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<section name="PlanAhead Usage" visible="true">
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<property name="DesignMode" value="GateLvl" type="DesignMode"/>
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
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