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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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top/b200/coregen/chipscope_ila_128.veo
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.veo
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_ila_128 YourInstanceName (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK), // IN
.TRIG0(TRIG0) // IN BUS [127:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------